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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id o16-20020a1709061b1000b00734b2169222sm2363778ejg.186.2022.08.19.07.02.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 07:02:51 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH 0/4] riscv: Introduce support for defining instructions Date: Fri, 19 Aug 2022 16:02:46 +0200 Message-Id: <20220819140250.3892995-1-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_070257_828959_C5F54857 X-CRM114-Status: GOOD ( 11.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When compiling with toolchains that haven't yet been taught about new instructions we need to encode them ourselves. This series creates a new file where support for instruction definitions can evolve. For starters the file is initiated with a macro for R-type encodings. The series then applies the R-type encoding macro to all instances of hard coded instruction definitions in KVM. Not only should using instruction encoding macros improve readability and maintainability of code, but we should also gain potential for more optimized code after compilation as the compiler will have control over the input and output registers used, which may provide more opportunities for inlining. I grepped for other places we may want to use these macros and the only place I found was ALT_CMO_OP(), but I didn't dare touch it :-) I do suggest we apply this to the Svinal support [1] as we won't want to frustrate the compiler's inlining efforts with hard coded register selection. [1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/ Andrew Jones (4): riscv: Add X register names to gpr-nums riscv: Introduce support for defining instructions riscv: KVM: Apply insn-def to hfence encodings riscv: KVM: Apply insn-def to hlv encodings arch/riscv/Kconfig | 3 + arch/riscv/include/asm/gpr-num.h | 8 ++ arch/riscv/include/asm/insn-def.h | 104 ++++++++++++++++++++++++++ arch/riscv/kvm/tlb.c | 117 ++++-------------------------- arch/riscv/kvm/vcpu_exit.c | 29 ++------ 5 files changed, 133 insertions(+), 128 deletions(-) create mode 100644 arch/riscv/include/asm/insn-def.h