From patchwork Mon Oct 10 12:27:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13002562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF316C4332F for ; Mon, 10 Oct 2022 12:27:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=RZEV7WoDrmStpD3TFf/8+alJDjGFCOuG4mq8CXQYwgQ=; b=fP9/oF4w9yRPTQ MjHLl5vE7Z8bZqqBLBQY0GkJkHS18Xm4B1DlBYXpwUCmTsTJL19yPlpUFSpS1jFg/apDvSn1NHEs6 uWJE1OQJoHGtl1X1HEEuoXucpYBrv5iRHA4IdMsM2xjGMylLPBs0I5iW2zfoe4dGMrrB5T0VSTq6n WDFQdaO+6RHpEF9RMfMVj4tSBs2oG6DMX40DZT2HbOVAqbKV1VHy6fFJsfvHEDC0TRpnTbFcf+oNO +gqykPRmexVs1pL59inomM9vGEJma6hSEy7oVL2+upFAkHb/ew41IZ1/K5P8CsIAK1EINNgaaj7sw vR3DlATbWCQVdx/2AvHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ohrsi-000ph0-QO; Mon, 10 Oct 2022 12:27:40 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ohrsf-000pfH-9D for linux-riscv@lists.infradead.org; Mon, 10 Oct 2022 12:27:38 +0000 Received: from p5b1274fa.dip0.t-ipconnect.de ([91.18.116.250] helo=phil.fritz.box) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ohrsW-0001kg-Od; Mon, 10 Oct 2022 14:27:28 +0200 From: Heiko Stuebner To: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org, mark.rutland@arm.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor.Dooley@microchip.com, ajones@ventanamicro.com, Heiko Stuebner Subject: [PATCH v5 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Date: Mon, 10 Oct 2022 14:27:24 +0200 Message-Id: <20221010122726.2405153-1-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221010_052737_341523_5F7D14D7 X-CRM114-Status: GOOD ( 10.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension but not completely identical, so this series changes in v5: - add received Reviews - fix sbi caching wrt. negative values (Drew) - add comment about specific c9xx arch- and imp-ids (Conor) changes in v4: - add new patch to cache sbi mvendor, march and mimp-ids (Atish) - errata dependencies in one line (Conor) - make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish) changes in v3: - improve commit message (Atish, Conor) - IS_ENABLED and BIT() in errata probe (Conor) The change depends on my cpufeature/t-head errata probe cleanup series [1]. changes in v2: - use alternatives for the CSR access - make the irq num selection a bit nicer There is of course a matching opensbi-part whose most recent implementation can be found on [0]. [0] https://patchwork.ozlabs.org/project/opensbi/cover/20221004164227.1381825-1-heiko@sntech.de [1] https://lore.kernel.org/all/20220905111027.2463297-1-heiko@sntech.de/ Heiko Stuebner (2): RISC-V: Cache SBI vendor values drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores arch/riscv/Kconfig.erratas | 13 +++++++++++ arch/riscv/errata/thead/errata.c | 19 ++++++++++++++++ arch/riscv/include/asm/errata_list.h | 16 +++++++++++++- arch/riscv/kernel/sbi.c | 30 ++++++++++++++++++++++--- drivers/perf/riscv_pmu_sbi.c | 33 +++++++++++++++++++--------- 5 files changed, 97 insertions(+), 14 deletions(-)