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Tue, 25 Oct 2022 15:06:43 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:1d2a:d2a2:361e:a475]) by smtp.gmail.com with ESMTPSA id l18-20020a05600c1d1200b003a342933727sm210534wms.3.2022.10.25.15.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 15:06:42 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Olof Johansson Cc: Conor Dooley , Samuel Holland , soc@kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 0/2] RZ/G2UL separate out SoC specific parts Date: Tue, 25 Oct 2022 23:06:27 +0100 Message-Id: <20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221025_150646_223013_DDDBD45D X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Hi All, This patch series aims to split up the RZ/G2UL SoC DTSI into common parts so that this can be shared with the RZ/Five SoC. Implementation is based on the discussion [0] where I have used option#2. The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five (r9a07g043f.dtsi) r9a07g043f.dtsi (RZ/Five SoC DTSI) will look something like below: #include #define SOC_PERIPHERAL_IRQ(nr) (nr + 32) #include / { ... ... }; Although patch#2 can be merged into patch#1 just wanted to keep them separated for easier review. Changes for v2: - Fixed review comments pointed by Geert - Changed the SOC_PERIPHERAL_IRQ() macro RFC-> RESEND RFC * Patches rebased on top of renesas-arm-dt-for-v6.2 [1]. RESEND: - https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221017091201.199457-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ RFC: - https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/ [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/?h=renesas-arm-dt-for-v6.2 Cheers, Prabhakar Lad Prabhakar (2): arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 347 ++++++++---------- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++ .../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +- 3 files changed, 220 insertions(+), 201 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi