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[81.185.174.238]) by smtp.gmail.com with ESMTPSA id a6-20020a1cf006000000b003ed4f6c6234sm1963364wmb.23.2023.03.16.06.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 06:17:16 -0700 (PDT) From: Alexandre Ghiti To: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Frank Rowand , Mike Rapoport , Andrew Morton , Anup Patel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-mm@kvack.org Cc: Alexandre Ghiti Subject: [PATCH v8 0/4] riscv: Use PUD/P4D/PGD pages for the linear mapping Date: Thu, 16 Mar 2023 14:17:07 +0100 Message-Id: <20230316131711.1284451-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230316_131721_458860_7B12A91F X-CRM114-Status: GOOD ( 16.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patchset intends to improve tlb utilization by using hugepages for the linear mapping. As reported by Anup in v6, when STRICT_KERNEL_RWX is enabled, we must take care of isolating the kernel text and rodata so that they are not mapped with a PUD mapping which would then assign wrong permissions to the whole region: it is achieved by introducing a new memblock API. Another patch makes use of this new API in arm64 which used some sort of hack to solve this issue: it was built/boot tested successfully. base-commit-tag: v6.3-rc1 v8: - Fix rv32, as reported by Anup - Do not modify memblock_isolate_range and fixes comment, as suggested by Mike - Use the new memblock API for crash kernel too in arm64, as suggested by Andrew - Fix arm64 double mapping (which to me did not work in v7), but ends up not being pretty at all, will wait for comments from arm64 reviewers, but this patch can easily be dropped if they do not want it. v7: - Fix Anup bug report by introducing memblock_isolate_memory which allows us to split the memblock mappings and then avoid to map the the PUD which contains the kernel as read only - Add a patch to arm64 to use this newly introduced API v6: - quiet LLVM warning by casting phys_ram_base into an unsigned long v5: - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks Conor - Add RB from Andrew v4: - Rebase on top of v6.2-rc3, as noted by Conor - Add Acked-by Rob v3: - Change the comment about initrd_start VA conversion so that it fits ARM64 and RISCV64 (and others in the future if needed), as suggested by Rob v2: - Add a comment on why RISCV64 does not need to set initrd_start/end that early in the boot process, as asked by Rob Alexandre Ghiti (4): riscv: Get rid of riscv_pfn_base variable mm: Introduce memblock_isolate_memory arm64: Make use of memblock_isolate_memory for the linear mapping riscv: Use PUD/P4D/PGD pages for the linear mapping arch/arm64/mm/mmu.c | 25 +++++++++++------ arch/riscv/include/asm/page.h | 19 +++++++++++-- arch/riscv/mm/init.c | 53 ++++++++++++++++++++++++++++------- arch/riscv/mm/physaddr.c | 16 +++++++++++ drivers/of/fdt.c | 11 ++++---- include/linux/memblock.h | 1 + mm/memblock.c | 20 +++++++++++++ 7 files changed, 119 insertions(+), 26 deletions(-)