From patchwork Fri Mar 17 11:35:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13178968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B40EC6FD1D for ; Fri, 17 Mar 2023 11:36:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ObwxTOp075szF9kM0bS8dHbG5uiGl59qJf+Eh89CaKc=; b=xn6YyrKqfDe4b/ AkIeQYsvjD6G7fkWHj8iAYtRdehx1OcYkAqNP3pILrkocCLLjOseFQhkULy3YpVXrPEKGS9t6od6p yXq8r7Nyf+Aegjqki3DKg7Gh/EEpZMp+DqPzmgUYSkr4A9w2o6mhyAcoSjYmklx4WtUbiQC76/pe8 1hlRyD3eyWyNVHJJ+46uAcVJRg6FQiJOUkAK5ZP3BjhPkCPPRHFsEwLy/OaTYdtCy5qeJ5HVRj4pM ZuMQ2H+kPKeQq6D3AZbU2GpaIxOC+SzhM98ea7MCLicZ1PpUsIQEuLh8Wz7rN/V5XvvT3rUjy76XR AWONL2HuCxWqt1z3mNrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pd8Nl-0024pO-1i; Fri, 17 Mar 2023 11:36:25 +0000 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pd8Ni-0024nY-2i for linux-riscv@lists.infradead.org; Fri, 17 Mar 2023 11:36:24 +0000 Received: by mail-pl1-x629.google.com with SMTP id k2so4979431pll.8 for ; Fri, 17 Mar 2023 04:36:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1679052978; h=message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EJDBG7kBBHxN4whOw8CwS1rep1qG2OJuyYu9ivjuoOk=; b=ASKdAvlndZMl4rdtER/7MdXa3ELTowJ/5bUURqeAo2jxbQ1oSWiRJqT6pz/jOfAr0o n0t8s6P8ST0kUmPV4cQRREpwfhdLovGmkHmScfiX20AoKX364Qt34+cfC3piav18M95c zQlqdfI2ZtmXxWXjS1Nvu7QtuVpQyTpNs7tVrXXdyYmID3iODkuGj8rQKoAhfP8BmF2P 7TfzafE9MZ37FFQo4Gwy82FGz1M8i7i4+F9Ko5a0y0gRBm5xCHEJee8eYqHr0jXDXhtG 7YGBobEVbrKaFrmghqj45Pqfw1AdP9T2VxTyT7OunQY4tdDsbI99YgyBozPvDOOF5eil 2SUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679052978; h=message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EJDBG7kBBHxN4whOw8CwS1rep1qG2OJuyYu9ivjuoOk=; b=xY+rVaPZ0rJkWL1dNfjMVYXIrA+7+tpYbhrwdiUFVTj2FAo5rgnUyDoTZux4qOmGl2 SHlxM2S+G7APwZlA517iTbCzsEcTR3lolk3qMsGpVItuz4229LeGBpd1Ixg5gdvRzxL4 ygLVvDSVbQVcT4qykyTKcfdAQIS4HgajsK8We4wmCMo1z6B+Rg9x8/P17z24jGj3md6n Wei9ZTJP9kIIS0JpPw+i4DEVS8HNsYD3mO+nk+BzubF1Nh6DWpf7SsUcnPoasQLN4Og2 9la7OGHIgszEX0GhDVsZNzY4uVC6CAfquGUOl/+OJkyoq9mah+Qwl6jvMn3keW5t94di cohA== X-Gm-Message-State: AO0yUKWd+0UjwreHUhxJv+miZhqahMliXVJWF0zoAndPryBhsVPFdFbA LsG3Dkebe9z+AufWwV5VYbdW08PpLanKHNfbQVTFpdej5kLDTG0T6dFrATLeSt+jk40mevrULfz qrslUDpuTn55MECrHEjZzf/+aSeV3RPqUNcVp0X4NJTH6jts+fW6G94jeqFgBesgsFG+JJiIsVl 8Hqwn9Ql8yR1l/ X-Google-Smtp-Source: AK7set+rTZY+uRb998wvZMyisVnvIRiKtTFiLAHr7HIt9Xb91qYyx5HYH3MEYZQ0JVZo7tSQkZfOhg== X-Received: by 2002:a17:90b:1b4e:b0:234:c030:7c7f with SMTP id nv14-20020a17090b1b4e00b00234c0307c7fmr3204248pjb.18.1679052978375; Fri, 17 Mar 2023 04:36:18 -0700 (PDT) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id n63-20020a17090a2cc500b0023d3845b02bsm1188740pjd.45.2023.03.17.04.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 04:36:17 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Nathan Chancellor , Nick Desaulniers , Tom Rix Subject: [PATCH -next v15 00/19] riscv: Add vector ISA support Date: Fri, 17 Mar 2023 11:35:19 +0000 Message-Id: <20230317113538.10878-1-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230317_043622_879449_37193B63 X-CRM114-Status: GOOD ( 25.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patchset is implemented based on vector 1.0 spec to add vector support in riscv Linux kernel. There are some assumptions for this implementations. 1. We assume all harts has the same ISA in the system. 2. We disable vector in both kernel andy user space [1] by default. Only enable an user's vector after an illegal instruction trap where it actually starts executing vector (the first-use trap [2]). 3. We detect "riscv,isa" to determine whether vector is support or not. We defined a new structure __riscv_v_ext_state in struct thread_struct to save/restore the vector related registers. It is used for both kernel space and user space. - In kernel space, the datap pointer in __riscv_v_ext_state will be allocated to save vector registers. - In user space, - In signal handler of user space, the structure is placed right after __riscv_ctx_hdr, which is embedded in fp reserved aera. This is required to avoid ABI break [2]. And datap points to the end of __riscv_v_ext_state. - In ptrace, the data will be put in ubuf in which we use riscv_vr_get()/riscv_vr_set() to get or set the __riscv_v_ext_state data structure from/to it, datap pointer would be zeroed and vector registers will be copied to the address right after the __riscv_v_ext_state structure in ubuf. This patchset is rebased to v6.3-rc1 and it is tested by running several vector programs simultaneously. It delivers signals correctly in a test where we can see a valid ucontext_t in a signal handler, and a correct V context returing back from it. And the ptrace interface is tested by PTRACE_{GET,SET}REGSET. Lastly, KVM is tested by running above tests in a guest using the same kernel image. All tests are done on an rv64gcv virt QEMU. Note: please apply the patch at [4] due to a regression introduced by commit 596ff4a09b89 ("cpumask: re-introduce constant-sized cpumask optimizations") before testing the series. Specail thanks to Conor and Vineet for kindly giving help on- and off-list. Source tree: https://github.com/sifive/riscv-linux/tree/riscv/for-next/vector-v15 Links: - [1] https://lore.kernel.org/all/20220921214439.1491510-17-stillson@rivosinc.com/ - [2] https://lore.kernel.org/all/73c0124c-4794-6e40-460c-b26df407f322@rivosinc.com/T/#u - [3] https://lore.kernel.org/all/20230128082847.3055316-1-apatel@ventanamicro.com/ - [4] https://lore.kernel.org/all/CAHk-=wiAxtKyxs6BPEzirrXw1kXJ-7ZyGpgOrbzhmC=ud-6jBA@mail.gmail.com/ --- Changelog V15 - Rebase to risc-v -next (v6.3-rc1) - Make V depend on FD in Kconfig according to the spec and shut off v properly. - Fix a syntax error for clang build. But mark RISCV_ISA_V GAS only due to https://reviews.llvm.org/D123515 - Use scratch reg in inline asm instead of t4. - Refine code. - Cleanup per-patch changelogs. Changelog V14 - Rebase to risc-v -next (v6.2-rc7) - Use TOOLCHAIN_HAS_V to detect if we can enable Vector. And refine KBUILD_CFLAGS to remove v from default compile option. - Drop illegal instruction handling patch in kvm and leave it to a independent series[3]. The series has merged into 6.3-rc1 - Move KVM_RISCV_ISA_EXT_V to the end of enum to prevent potential ABI breaks. - Use PT_SIZE_ON_STACK instead of PT_SIZE to fit alignment. Also, remove panic log from v13 (15/19) because it is no longer relevant. - Rewrite insn_is_vector for better structuring (change if-else chain to a switch) - Fix compilation error in the middle of the series - Validate size of the alternative signal frame if V is enabled whenever: - The user call sigaltstack to update altstack - A signal is being delivered - Rename __riscv_v_state to __riscv_v_ext_state. - Add riscv_v_ prefix and rename rvv appropriately - Organize riscv_v_vsize setup code into vector.c - Address the issue mentioned by Heiko on !FPU case - Honor orignal authors that got changed accidentally in v13 4,5,6 Changelog V13 - Rebase to latest risc-v next (v6.2-rc1) - vineetg: Re-organize the series to comply with bisect-ability - andy.chiu: Improve task switch with inline assembly - Re-structure the signal frame to avoid user ABI break. - Implemnt first-use trap and drop prctl for per-task V state enablement. Also, redirect this trap from hs to vs for kvm setup. - Do not expose V context in ptrace/sigframe until the task start using V. But still reserve V context for size ofsigframe reported by auxv. - Drop the kernel mode vector and leave it to another (future) series. Changelog V12 (Chris) - rebases to some point after v5.18-rc6 - add prctl to control per-process V state Chnagelog V10 - Rebase to v5.18-rc6 - Merge several patches - Refine codes - Fix bugs - Add kvm vector support Changelog V9 - Rebase to v5.15 - Merge several patches - Refine codes - Fix a kernel panic issue Changelog V8 - Rebase to v5.14 - Refine struct __riscv_v_ext_state with struct __riscv_ctx_hdr - Refine has_vector into a static key - Defined __reserved space in struct sigcontext for vector and future extensions Changelog V7 - Add support for kernel mode vector - Add vector extension XOR implementation - Optimize task switch codes of vector - Allocate space for vector registers in start_thread() - Fix an illegal instruction exception when accessing vlenb - Optimize vector registers initialization - Initialize vector registers with proper vsetvli then it can work normally - Refine ptrace porting due to generic API changed - Code clean up Changelog V6 - Replace vle.v/vse.v instructions with vle8.v/vse8.v based on 0.9 spec - Add comments based on mailinglist feedback - Fix rv32 build error Changelog V5 - Using regset_size() correctly in generic ptrace - Fix the ptrace porting - Fix compile warning Changelog V4 - Support dynamic vlen - Fix bugs: lazy save/resotre, not saving vtype - Update VS bit offset based on latest vector spec - Add new vector csr based on latest vector spec - Code refine and removed unused macros Changelog V3 - Rebase linux-5.6-rc3 and tested with qemu - Seperate patches with Anup's advice - Give out a ABI puzzle with unlimited vlen Changelog V2 - Fixup typo "vecotr, fstate_save->vstate_save". - Fixup wrong saved registers' length in vector.S. - Seperate unrelated patches from this one. Andy Chiu (3): riscv: Allocate user's vector context in the first-use trap riscv: signal: check fp-reserved words unconditionally riscv: signal: validate altstack to reflect Vector Greentime Hu (9): riscv: Add new csr defines related to vector extension riscv: Clear vector regfile on bootup riscv: Introduce Vector enable/disable helpers riscv: Introduce riscv_v_vsize to record size of Vector context riscv: Introduce struct/helpers to save/restore per-task Vector state riscv: Add task switch support for vector riscv: Add ptrace vector support riscv: signal: Add sigcontext save/restore for vector riscv: prevent stack corruption by reserving task_pt_regs(p) early Guo Ren (4): riscv: Rename __switch_to_aux() -> fpu riscv: Extending cpufeature.c to detect V-extension riscv: Disable Vector Instructions for kernel itself riscv: Enable Vector code to be built Vincent Chen (3): riscv: signal: Report signal frame size to userspace via auxv riscv: kvm: Add V extension to KVM ISA riscv: KVM: Add vector lazy save/restore support arch/riscv/Kconfig | 20 ++ arch/riscv/Makefile | 6 +- arch/riscv/include/asm/csr.h | 18 +- arch/riscv/include/asm/elf.h | 9 + arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/insn.h | 29 +++ arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/include/asm/kvm_vcpu_vector.h | 77 ++++++++ arch/riscv/include/asm/processor.h | 3 + arch/riscv/include/asm/switch_to.h | 9 +- arch/riscv/include/asm/thread_info.h | 3 + arch/riscv/include/asm/vector.h | 179 ++++++++++++++++++ arch/riscv/include/uapi/asm/auxvec.h | 1 + arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 8 + arch/riscv/include/uapi/asm/ptrace.h | 39 ++++ arch/riscv/include/uapi/asm/sigcontext.h | 16 +- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpufeature.c | 13 ++ arch/riscv/kernel/entry.S | 6 +- arch/riscv/kernel/head.S | 41 ++++- arch/riscv/kernel/process.c | 18 ++ arch/riscv/kernel/ptrace.c | 70 +++++++ arch/riscv/kernel/setup.c | 3 + arch/riscv/kernel/signal.c | 221 ++++++++++++++++++++--- arch/riscv/kernel/traps.c | 14 +- arch/riscv/kernel/vector.c | 111 ++++++++++++ arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 31 ++++ arch/riscv/kvm/vcpu_vector.c | 177 ++++++++++++++++++ include/uapi/linux/elf.h | 1 + 31 files changed, 1081 insertions(+), 48 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_vector.h create mode 100644 arch/riscv/include/asm/vector.h create mode 100644 arch/riscv/kernel/vector.c create mode 100644 arch/riscv/kvm/vcpu_vector.c