From patchwork Wed Jul 19 11:35:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13318831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F282C0015E for ; Wed, 19 Jul 2023 11:36:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=56/81jJ9wg89GOYZmTa9U9glFc+qi6zl4+CtuPybbwI=; b=GSAJoqlMQIXLSl gIaLeIiBnuvTrtRhVb30qQnjF+kvEYjg4qGoP67V+Yg6i6fJ0WNwNtGtHFMvavVtbu6J8Sx/Mrh4C pM0zmhrtPlMYsprRhJSSKQiPhTqM1Y/ZNo420Cig6E7H4ZJoYIEpkIu0YFVYDJUDZW0OUeGqscRbn uP34gRNndQzWfdpM7EV+A9ml8bsXb5TLoAeLH9CIfXsk+I31wrunhONHgqIk05hCVRuJNQyQr5Py6 UwXdgZnjMsiM3fJhSX88NaOv4+ESdH8nF9ALkoHjNA1//BDooSJhMhvQpCkX7cgLBYcQCynEuy3Dv T8TOROl13y6VopMkjREw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qM5TL-007Frf-2F; Wed, 19 Jul 2023 11:35:59 +0000 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qM5TI-007Fqn-1c for linux-riscv@lists.infradead.org; Wed, 19 Jul 2023 11:35:58 +0000 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-666e916b880so4515834b3a.2 for ; Wed, 19 Jul 2023 04:35:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689766554; x=1690371354; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=6nC1A7cDnBddvNe2esAWde6LHxe7McCx3js8WRqxi4o=; b=gpZeRU0XDArYb+OFvtQnaTPEutuLJbVdi/GBSYnEDtHgFZnJEJriE9o9RopjaQVXjs TgA00Of56dCtRDfQOkyurnUkLGRyliJrUqj8eQGZh4UcwZBYH8Uv6Ync5CfHndndvfSq JYMWVKwx24XaxqFJKI3F13b235CpnHaqzvbrrn2eXGafG3xMe1AiJkt3F08/c2ykZVjR ISORRRtDWsgKxBafnY0/8n06H1ViMo8CHiiUPNb0cXLcNjNSgEnFkOqjs9AF6yKcdVzF o0c4dOS4J8ha9Si5f3m5LEjjtmv0tjJsCmtdpmBIrvjMiKXlzeuiRtoifkgRm1q3xxcL 6+UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689766554; x=1690371354; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6nC1A7cDnBddvNe2esAWde6LHxe7McCx3js8WRqxi4o=; b=IDtGuI0l6vclC4yYebl3PnOk/Hd27J8Jbx4d54F6ZnXEAFmg92R5t6tP64LA0JdCCZ NhOXW5lYOox+e/g++XIT7aMS6yKNRNbWyyUNtfxoRdgACPlKa2IyeUf/mg/RqVHSi4zz gezXLJhnjR+brS4ueh20xvbwzFhJdXb1nkeHs64BFpq7c1CBUGAcsrUjwzylj/Cc0NZc Ua9c/mQvri3syhT+vf6etulfT6a8gXOx0dWtWaZCDI0OEv5dxENjOcsA5uWi6vPGs5MN G30dmTcON/GJ2buLEzyiWZru2OX9dI7mVUojw0yulRFcP/t4qIXuEOkbolU8T1biQYMZ sk9A== X-Gm-Message-State: ABy/qLb4Rr21RmZDi8Sn87klRIgXOJ9S1WbnZUP+YpHNe5J38iDJh8es AP7axZWW4LUB0CH5IV6fZe/64Q== X-Google-Smtp-Source: APBJJlE4f9hCnGXFi7+wVx7g55pXhzYORdWUzThCEchgqGrktpR51ViDhaPlb5oJfpuj/MjYnad4jw== X-Received: by 2002:a05:6a00:10c9:b0:653:b76d:4d62 with SMTP id d9-20020a056a0010c900b00653b76d4d62mr19575543pfu.24.1689766554080; Wed, 19 Jul 2023 04:35:54 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.130]) by smtp.gmail.com with ESMTPSA id j10-20020aa783ca000000b00669c99d05fasm3050408pfn.150.2023.07.19.04.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 04:35:53 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Subject: [PATCH v6 00/14] Linux RISC-V AIA Support Date: Wed, 19 Jul 2023 17:05:28 +0530 Message-Id: <20230719113542.2293295-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230719_043556_565264_DD1D5812 X-CRM114-Status: GOOD ( 20.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , devicetree@vger.kernel.org, Saravana Kannan , Anup Patel , linux-kernel@vger.kernel.org, Atish Patra , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The RISC-V AIA specification is now frozen as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf At a high-level, the AIA specification adds three things: 1) AIA CSRs - Improved local interrupt support 2) Incoming Message Signaled Interrupt Controller (IMSIC) - Per-HART MSI controller - Support MSI virtualization - Support IPI along with virtualization 3) Advanced Platform-Level Interrupt Controller (APLIC) - Wired interrupt controller - In MSI-mode, converts wired interrupt into MSIs (i.e. MSI generator) - In Direct-mode, injects external interrupts directly into HARTs For an overview of the AIA specification, refer the AIA virtualization talk at KVM Forum 2022: https://static.sched.com/hosted_files/kvmforum2022/a1/AIA_Virtualization_in_KVM_RISCV_final.pdf https://www.youtube.com/watch?v=r071dL8Z0yo To test this series, use QEMU v7.2 (or higher) and OpenSBI v1.2 (or higher). These patches can also be found in the riscv_aia_v6 branch at: https://github.com/avpatel/linux.git Changes since v5: - Rebased on Linux-6.5-rc2 - Updated the overall series to ensure that only IPI, timer, and INTC drivers are probed very early whereas rest of the interrupt controllers (such as PLIC, APLIC, and IMISC) are probed as regular platform drivers. - Renamed riscv_fw_parent_hartid() to riscv_get_intc_hartid() - New PATCH1 to add fw_devlink support for msi-parent DT property - New PATCH2 to ensure all INTC suppliers are initialized which in-turn fixes the probing issue for PLIC, APLIC and IMSIC as platform driver - New PATCH3 to use platform driver probing for PLIC - Re-structured the IMSIC driver into two separate drivers: early and platform. The IMSIC early driver (PATCH7) only initialized IMSIC state and provides IPIs whereas the IMSIC platform driver (PATCH8) is probed provides MSI domain for platform devices. - Re-structure the APLIC platform driver into three separe sources: main, direct mode, and MSI mode. Changes since v4: - Rebased on Linux-6.5-rc1 - Added "Dependencies" in the APLIC bindings (PATCH6 in v4) - Dropped the PATCH6 which was changing the IOMMU DMA domain APIs - Dropped use of IOMMU DMA APIs in the IMSIC driver (PATCH4) Changes since v3: - Rebased on Linux-6.4-rc6 - Droped PATCH2 of v3 series instead we now set FWNODE_FLAG_BEST_EFFORT via IRQCHIP_DECLARE() - Extend riscv_fw_parent_hartid() to support both DT and ACPI in PATCH1 - Extend iommu_dma_compose_msi_msg() instead of adding iommu_dma_select_msi() in PATCH6 - Addressed Conor's comments in PATCH3 - Addressed Conor's and Rob's comments in PATCH7 Changes since v2: - Rebased on Linux-6.4-rc1 - Addressed Rob's comments on DT bindings patches 4 and 8. - Addessed Marc's comments on IMSIC driver PATCH5 - Replaced use of OF apis in APLIC and IMSIC drivers with FWNODE apis this makes both drivers easily portable for ACPI support. This also removes unnecessary indirection from the APLIC and IMSIC drivers. - PATCH1 is a new patch for portability with ACPI support - PATCH2 is a new patch to fix probing in APLIC drivers for APLIC-only systems. - PATCH7 is a new patch which addresses the IOMMU DMA domain issues pointed out by SiFive Changes since v1: - Rebased on Linux-6.2-rc2 - Addressed comments on IMSIC DT bindings for PATCH4 - Use raw_spin_lock_irqsave() on ids_lock for PATCH5 - Improved MMIO alignment checks in PATCH5 to allow MMIO regions with holes. - Addressed comments on APLIC DT bindings for PATCH6 - Fixed warning splat in aplic_msi_write_msg() caused by zeroed MSI message in PATCH7 - Dropped DT property riscv,slow-ipi instead will have module parameter in future. Anup Patel (14): RISC-V: Add riscv_get_intc_hartid() function of: property: Add fw_devlink support for msi-parent drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized irqchip/sifive-plic: Use platform driver probing for PLIC irqchip/riscv-intc: Add support for RISC-V AIA dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller irqchip: Add RISC-V incoming MSI controller early driver irqchip/riscv-imsic: Add support for platform MSI irqdomain irqchip/riscv-imsic: Add support for PCI MSI irqdomain dt-bindings: interrupt-controller: Add RISC-V advanced PLIC irqchip: Add RISC-V advanced PLIC driver for direct-mode irqchip/riscv-aplic: Add support for MSI-mode RISC-V: Select APLIC and IMSIC drivers MAINTAINERS: Add entry for RISC-V AIA drivers .../interrupt-controller/riscv,aplic.yaml | 172 ++++++ .../interrupt-controller/riscv,imsics.yaml | 172 ++++++ MAINTAINERS | 14 + arch/riscv/Kconfig | 2 + arch/riscv/include/asm/processor.h | 4 +- arch/riscv/kernel/cpu.c | 19 +- drivers/irqchip/Kconfig | 25 +- drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-riscv-aplic-direct.c | 326 +++++++++++ drivers/irqchip/irq-riscv-aplic-main.c | 240 ++++++++ drivers/irqchip/irq-riscv-aplic-main.h | 53 ++ drivers/irqchip/irq-riscv-aplic-msi.c | 285 ++++++++++ drivers/irqchip/irq-riscv-imsic-early.c | 258 +++++++++ drivers/irqchip/irq-riscv-imsic-platform.c | 328 +++++++++++ drivers/irqchip/irq-riscv-imsic-state.c | 523 ++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 67 +++ drivers/irqchip/irq-riscv-intc.c | 46 +- drivers/irqchip/irq-sifive-plic.c | 15 +- drivers/of/property.c | 32 ++ include/linux/irqchip/riscv-aplic.h | 119 ++++ include/linux/irqchip/riscv-imsic.h | 86 +++ 21 files changed, 2773 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml create mode 100644 drivers/irqchip/irq-riscv-aplic-direct.c create mode 100644 drivers/irqchip/irq-riscv-aplic-main.c create mode 100644 drivers/irqchip/irq-riscv-aplic-main.h create mode 100644 drivers/irqchip/irq-riscv-aplic-msi.c create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h create mode 100644 include/linux/irqchip/riscv-aplic.h create mode 100644 include/linux/irqchip/riscv-imsic.h