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([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:28 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 00/10] RISC-V: KVM: change get_reg/set_reg error codes Date: Thu, 3 Aug 2023 11:00:12 -0300 Message-ID: <20230803140022.399333-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230803_070032_593528_69E75F78 X-CRM114-Status: UNSURE ( 9.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi, This version has changes in the document patch, as suggested by Andrew in v2. It also has a new patch (patch 9) that handles error code changes in vcpu_vector.c. Patches rebased on top of kvm_riscv_queue. Changes from v2: - patch 9 (new): - change kvm error codes for vector registers - patch 10 (former 9): - rewrite EBUSY doc to mention that the error code indicates that it is not allowed to change the reg val after the vcpu started. - v2 link: https://lore.kernel.org/kvm/20230801222629.210929-1-dbarboza@ventanamicro.com/ Andrew Jones (1): RISC-V: KVM: Improve vector save/restore errors Daniel Henrique Barboza (9): RISC-V: KVM: return ENOENT in *_one_reg() when reg is unknown RISC-V: KVM: use ENOENT in *_one_reg() when extension is unavailable RISC-V: KVM: do not EOPNOTSUPP in set_one_reg() zicbo(m|z) RISC-V: KVM: do not EOPNOTSUPP in set KVM_REG_RISCV_TIMER_REG RISC-V: KVM: use EBUSY when !vcpu->arch.ran_atleast_once RISC-V: KVM: avoid EBUSY when writing same ISA val RISC-V: KVM: avoid EBUSY when writing the same machine ID val RISC-V: KVM: avoid EBUSY when writing the same isa_ext val docs: kvm: riscv: document EBUSY in KVM_SET_ONE_REG Documentation/virt/kvm/api.rst | 2 + arch/riscv/kvm/aia.c | 4 +- arch/riscv/kvm/vcpu_fp.c | 12 +++--- arch/riscv/kvm/vcpu_onereg.c | 68 +++++++++++++++++++++++----------- arch/riscv/kvm/vcpu_sbi.c | 16 ++++---- arch/riscv/kvm/vcpu_timer.c | 11 +++--- arch/riscv/kvm/vcpu_vector.c | 60 ++++++++++++++++-------------- 7 files changed, 104 insertions(+), 69 deletions(-)