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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id je15-20020a170903264f00b001b243a20f26sm10577756plb.273.2023.09.13.09.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 09:39:22 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Anup Patel Cc: Mayuresh Chitale , Andrew Jones , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v5 0/7] Risc-V Kvm Smstateen Date: Wed, 13 Sep 2023 22:08:58 +0530 Message-Id: <20230913163905.480819-1-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230913_093927_290030_2DC74838 X-CRM114-Status: GOOD ( 12.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series adds support to detect the Smstateen extension for both, the host and the guest vcpu. It also adds senvcfg and sstateen0 to the ONE_REG interface and the vcpu context save/restore. The motivation behind Smstateen from the spec (https://github.com/riscv/riscv-state-enable): "The implementation of optional RISC-V extensions has the potential to open covert channels between separate user threads, or between separate guest OSes running under a hypervisor. The problem occurs when an extension adds processor state---usually explicit registers, but possibly other forms of state---that the main OS or hypervisor is unaware of (and hence won’t context-switch) but that can be modified/written by one user thread or guest OS and perceived/ examined/read by another." Changes in v5: - Rebased on latest linux master Changes in v4: - Update commit description for patch 1 - Rebase to kvm_riscv_queue - Add reviewed-by tag Changes in v3: - Move DT bindings change to a separate patch - Move senvcfg/sstateen0 save/restore to separate function Changes in v2: - Add smstaeen description in riscv/extensions.yaml - Avoid line wrap at 80 chars Mayuresh Chitale (7): RISC-V: Detect Smstateen extension dt-bindings: riscv: Add smstateen entry RISC-V: KVM: Add kvm_vcpu_config RISC-V: KVM: Enable Smstateen accesses RISCV: KVM: Add senvcfg context save/restore RISCV: KVM: Add sstateen0 context save/restore RISCV: KVM: Add sstateen0 to ONE_REG .../devicetree/bindings/riscv/extensions.yaml | 6 ++ arch/riscv/include/asm/csr.h | 18 +++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/kvm_host.h | 18 +++++ arch/riscv/include/uapi/asm/kvm.h | 10 +++ arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kvm/vcpu.c | 70 +++++++++++++++---- arch/riscv/kvm/vcpu_onereg.c | 41 +++++++++++ 8 files changed, 152 insertions(+), 13 deletions(-)