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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Hi All, This patch series does the following: * Adds L2 cache node and marks the SoC as noncoherent * Enables IP blocks which were explicitly disabled and for which support is present * Enables the configs required for RZ/Five SoC Cheers, Prabhakar Lad Prabhakar (5): riscv: dts: renesas: r9a07g043f: Add L2 cache node riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node riscv: configs: defconfig: Enable configs required for RZ/Five SoC arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 13 +++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 23 -------- arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 55 +------------------ arch/riscv/configs/defconfig | 52 ++++++++++++++++++ 4 files changed, 67 insertions(+), 76 deletions(-)