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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id l12-20020a170902f68c00b001cc0f6028b8sm2969008plg.106.2023.11.02.05.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 05:01:35 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, tjytimi@163.com, alex@ghiti.fr, conor.dooley@microchip.com, ajones@ventanamicro.com, Yong-Xuan Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH v3 0/4] Add Svadu Extension Support Date: Thu, 2 Nov 2023 12:01:21 +0000 Message-Id: <20231102120129.11261-1-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231102_050138_635341_5238E3D9 X-CRM114-Status: UNSURE ( 9.10 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Svadu is a RISC-V extension for hardware updating of PTE A/D bits. This patch set adds support to enable Svadu extension for both host and guest OS. --- v3: - fix the control bit name to ADUE in PATCH1 and PATCH3 - update get-reg-list in PATCH4 v2: - add Co-developed-by: in PATCH1 - use riscv_has_extension_unlikely() to runtime patch the branch in PATCH1 - update dt-binding Yong-Xuan Wang (4): RISC-V: Detect and Enable Svadu Extension Support dt-bindings: riscv: Add Svadu Entry RISC-V: KVM: Add Svadu Extension Support for Guest/VM KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt .../devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/pgtable.h | 6 ++++++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_onereg.c | 1 + .../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++++++++++++++++++ 9 files changed, 38 insertions(+)