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([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:39 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 0/6] riscv: hwprobe: add Zicond, Zacas and Ztso support Date: Wed, 20 Dec 2023 16:57:16 +0100 Message-ID: <20231220155723.684081-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231220_075745_334563_143AB26A X-CRM114-Status: UNSURE ( 8.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series add support for a few more extensions that are present in the RVA22U64/RVA23U64 (either mandatory or optional) and that are useful for userspace: - Zicond - Zacas - Ztso Series currently based on riscv/for-next. --- Changes in V2: - Removed Zam which is not yet ratified - Link to v1: https://lore.kernel.org/linux-riscv/20231213113308.133176-1-cleger@rivosinc.com/ Clément Léger (6): riscv: add ISA extension parsing for Ztso riscv: hwprobe: export Ztso ISA extension dt-bindings: riscv: add Zacas ISA extension description riscv: add ISA extension parsing for Zacas riscv: hwprobe: export Zacas ISA extension riscv: hwprobe: export Zicond extension Documentation/arch/riscv/hwprobe.rst | 13 +++++++++++++ .../devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/sys_riscv.c | 3 +++ 6 files changed, 29 insertions(+)