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Wed, 03 Jan 2024 08:32:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IH+6GSIc7+Qig8DFanxr8PlU4r2+JepKfCBXAeWKp5WEN4cGQRs5a42dQlyEupGQsh2bh8+QQ== X-Received: by 2002:a17:902:db85:b0:1d3:bceb:ba88 with SMTP id m5-20020a170902db8500b001d3bcebba88mr9465681pld.11.1704299551251; Wed, 03 Jan 2024 08:32:31 -0800 (PST) Received: from localhost.localdomain ([2804:431:c7ec:911:6911:ca60:846:eb46]) by smtp.gmail.com with ESMTPSA id e12-20020a170902b78c00b001cfca7b8ee7sm23930425pls.99.2024.01.03.08.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 08:32:30 -0800 (PST) From: Leonardo Bras To: Will Deacon , Peter Zijlstra , Boqun Feng , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Leonardo Bras , Guo Ren , Andrea Parri , Geert Uytterhoeven , Ingo Molnar , Andrzej Hajda Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 0/5] Rework & improve riscv cmpxchg.h and atomic.h Date: Wed, 3 Jan 2024 13:31:58 -0300 Message-ID: <20240103163203.72768-2-leobras@redhat.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240103_083237_811981_58C03E96 X-CRM114-Status: GOOD ( 17.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org While studying riscv's cmpxchg.h file, I got really interested in understanding how RISCV asm implemented the different versions of {cmp,}xchg. When I understood the pattern, it made sense for me to remove the duplications and create macros to make it easier to understand what exactly changes between the versions: Instruction sufixes & barriers. Also, did the same kind of work on atomic.c. After that, I noted both cmpxchg and xchg only accept variables of size 4 and 8, compared to x86 and arm64 which do 1,2,4,8. Now that deduplication is done, it is quite direct to implement them for variable sizes 1 and 2, so I did it. Then Guo Ren already presented me some possible users :) I did compare the generated asm on a test.c that contained usage for every changed function, and could not detect any change on patches 1 + 2 + 3 compared with upstream. Pathes 4 & 5 were compiled-tested, merged with guoren/qspinlock_v11 and booted just fine with qemu -machine virt -append "qspinlock". (tree: https://gitlab.com/LeoBras/linux/-/commits/guo_qspinlock_v11) Latest tests happened based on this tree: https://github.com/guoren83/linux/tree/qspinlock_v12 Thanks! Leo Changes since squashed cmpxchg RFCv5: - Resend as v1 https://lore.kernel.org/all/20230810040349.92279-2-leobras@redhat.com/ Changes since squashed cmpxchg RFCv4: - Added (__typeof__(*(p))) before returning from {cmp,}xchg, as done in current upstream, (possibly) fixing the bug from kernel test robot https://lore.kernel.org/all/20230809021311.1390578-2-leobras@redhat.com/ Changes since squashed cmpxchg RFCv3: - Fixed bug on cmpxchg macro for var size 1 & 2: now working - Macros for var size 1 & 2's lr.w and sc.w now are guaranteed to receive input of a 32-bit aligned address - Renamed internal macros from _mask to _masked for patches 4 & 5 - __rc variable on macros for var size 1 & 2 changed from register to ulong https://lore.kernel.org/all/20230804084900.1135660-2-leobras@redhat.com/ Changes since squashed cmpxchg RFCv2: - Removed rc parameter from the new macro: it can be internal to the macro - 2 new patches: cmpxchg size 1 and 2, xchg size 1 and 2 https://lore.kernel.org/all/20230803051401.710236-2-leobras@redhat.com/ Changes since squashed cmpxchg RFCv1: - Unified with atomic.c patchset - Rebased on top of torvalds/master (thanks Andrea Parri!) - Removed helper macros that were not being used elsewhere in the kernel. https://lore.kernel.org/all/20230419062505.257231-1-leobras@redhat.com/ https://lore.kernel.org/all/20230406082018.70367-1-leobras@redhat.com/ Changes since (cmpxchg) RFCv3: - Squashed the 6 original patches in 2: one for cmpxchg and one for xchg https://lore.kernel.org/all/20230404163741.2762165-1-leobras@redhat.com/ Changes since (cmpxchg) RFCv2: - Fixed macros that depend on having a local variable with a magic name - Previous cast to (long) is now only applied on 4-bytes cmpxchg https://lore.kernel.org/all/20230321074249.2221674-1-leobras@redhat.com/ Changes since (cmpxchg) RFCv1: - Fixed patch 4/6 suffix from 'w.aqrl' to '.w.aqrl', to avoid build error https://lore.kernel.org/all/20230318080059.1109286-1-leobras@redhat.com/ Leonardo Bras (5): riscv/cmpxchg: Deduplicate xchg() asm functions riscv/cmpxchg: Deduplicate cmpxchg() asm and macros riscv/atomic.h : Deduplicate arch_atomic.* riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 riscv/cmpxchg: Implement xchg for variables of size 1 and 2 arch/riscv/include/asm/atomic.h | 164 ++++++------- arch/riscv/include/asm/cmpxchg.h | 404 ++++++++++--------------------- 2 files changed, 200 insertions(+), 368 deletions(-) base-commit: 610a9b8f49fbcf1100716370d3b5f6f884a2835a