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Tue, 16 Jan 2024 18:54:33 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id rs3-20020a17090b2b8300b0028ceafb9124sm12553531pjb.51.2024.01.16.18.54.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 18:54:32 -0800 (PST) From: Charlie Jenkins Subject: [PATCH v8 0/2] riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Date: Tue, 16 Jan 2024 18:54:27 -0800 Message-Id: <20240116-fencei-v8-0-43a42134f021@rivosinc.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAGNBp2UC/23QTU7DMBAF4KtUXhM0M/4NK+6BWMT2mHpBUjnIA lW5O05F0whl+Sx/bzy+iplL5lm8nK6icM1znsYW3NNJhPMwfnCXY8uCgCQi2i7xGDh3qU8GonU qDSDa5UvhlL9vRW/vLZ/z/DWVn1tvxfX0r4LoXlGxg85zAIcYPCG9llynOY/hOUyfYm2ptJMSN klNUvCG5ODRYzqQ8iEJ5SblOtNq1I6kY28PpLpLBQjbwlU1GVVIlHwPOsoDqffSbVI3OQzIGqM loqPXmr3sN2maBIVomlVKhwNpdxIff2ubtC6BQcUYPfyTy7L8AiWfKZ37AQAA To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. [1] https://github.com/riscv/riscv-j-extension Signed-off-by: Charlie Jenkins --- Changes in v8: - Only flush icache if migrated to different cpu (Alex) - Move flushing to switch_to to catch per-thread flushing properly - Link to v7: https://lore.kernel.org/r/20240112-fencei-v7-0-78f0614e1db0@rivosinc.com Changes in v7: - Change "per_thread" parameter to "scope" and provide constants for the parameter. - Link to v6: https://lore.kernel.org/r/20240109-fencei-v6-0-04116e51445c@rivosinc.com Changes in v6: - Fixup documentation formatting - Link to v5: https://lore.kernel.org/r/20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com Changes in v5: - Minor documentation changes (Randy) - Link to v4: https://lore.kernel.org/r/20240107-fencei-v4-0-d4cf2fb905d3@rivosinc.com Changes in v4: - Add OFF flag to disallow fence.i in userspace (Atish) - Fix documentation issues (Atish) - Link to v3: https://lore.kernel.org/r/20231213-fencei-v3-0-b75158238eb7@rivosinc.com Changes in v3: - Check if value force_icache_flush set on thread, rather than in mm twice (Clément) - Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com Changes in v2: - Fix kernel-doc comment (Conor) - Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@rivosinc.com --- Charlie Jenkins (2): riscv: Include riscv_set_icache_flush_ctx prctl documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Documentation/arch/riscv/cmodx.rst | 96 ++++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + arch/riscv/include/asm/mmu.h | 4 ++ arch/riscv/include/asm/mmu_context.h | 3 ++ arch/riscv/include/asm/processor.h | 7 +++ arch/riscv/include/asm/switch_to.h | 17 +++++++ arch/riscv/mm/cacheflush.c | 67 +++++++++++++++++++++++++ arch/riscv/mm/context.c | 14 ++++-- include/uapi/linux/prctl.h | 6 +++ kernel/sys.c | 6 +++ 10 files changed, 218 insertions(+), 3 deletions(-) --- base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86 change-id: 20231117-fencei-f9f60d784fa0