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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3663ada0bdesm15693877f8f.113.2024.06.26.06.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 06:03:51 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrea Parri , Nathan Chancellor , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , Guo Ren , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2 00/10] Zacas/Zabha support and qspinlocks Date: Wed, 26 Jun 2024 15:03:37 +0200 Message-Id: <20240626130347.520750-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240626_060401_524194_F07FAFAC X-CRM114-Status: GOOD ( 14.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This implements [cmp]xchgXX() macros using Zacas and Zabha extensions and finally uses those newly introduced macros to add support for qspinlocks: note that this implementation of qspinlocks satisfies the forward progress guarantee. Thanks to Guo and Leonardo for their work! Changes in v2: - Add patch for Zabha dtbinding (Conor) - Fix cmpxchg128() build warnings missed in v1 - Make arch_cmpxchg128() fully ordered - Improve Kconfig help texts for both extensions (Conor) - Fix Makefile dependencies by requiring TOOLCHAIN_HAS_XXX (Nathan) - Fix compilation errors when the toolchain does not support the extensions (Nathan) - Fix C23 warnings about label at the end of coumpound statements (Nathan) - Fix Zabha and !Zacas configurations (Andrea) - Add COMBO spinlocks (Guo) - Improve amocas fully ordered operations by using .aqrl semantics and removing the fence rw, rw (Andrea) - Rebase on top "riscv: Fix fully ordered LR/SC xchg[8|16]() implementations" - Add ARCH_WEAK_RELEASE_ACQUIRE (Andrea) - Remove the extension version in march for LLVM since it is only required for experimental extensions (Nathan) - Fix cmpxchg128() implementation by adding both registers of a pair in the list of input/output operands Alexandre Ghiti (8): riscv: Implement cmpxchg32/64() using Zacas dt-bindings: riscv: Add Zabha ISA extension description riscv: Implement cmpxchg8/16() using Zabha riscv: Improve amocas.X use in cmpxchg() riscv: Implement arch_cmpxchg128() using Zacas riscv: Implement xchg8/16() using Zabha riscv: Improve amoswap.X use in xchg() riscv: Add qspinlock support based on Zabha extension Guo Ren (2): asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock asm-generic: ticket-lock: Add separate ticket-lock.h .../devicetree/bindings/riscv/extensions.yaml | 6 + .../locking/queued-spinlocks/arch-support.txt | 2 +- arch/riscv/Kconfig | 45 +++++ arch/riscv/Makefile | 6 + arch/riscv/include/asm/Kbuild | 4 +- arch/riscv/include/asm/cmpxchg.h | 188 ++++++++++++++---- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/spinlock.h | 39 ++++ arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/setup.c | 21 ++ include/asm-generic/qspinlock.h | 2 + include/asm-generic/spinlock.h | 87 +------- include/asm-generic/spinlock_types.h | 12 +- include/asm-generic/ticket_spinlock.h | 105 ++++++++++ 14 files changed, 385 insertions(+), 134 deletions(-) create mode 100644 arch/riscv/include/asm/spinlock.h create mode 100644 include/asm-generic/ticket_spinlock.h