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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac10c6c8dsm11087155ad.26.2024.06.28.02.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 02:37:15 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH v6 0/4] Add Svade and Svadu Extensions Support Date: Fri, 28 Jun 2024 17:37:04 +0800 Message-Id: <20240628093711.11716-1-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240628_023717_423216_2C7C4B0C X-CRM114-Status: GOOD ( 13.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Svade and Svadu extensions represent two schemes for managing the PTE A/D bit. When the PTE A/D bits need to be set, Svade extension intdicates that a related page fault will be raised. In contrast, the Svadu extension supports hardware updating of PTE A/D bits. This series enables Svade and Svadu extensions for both host and guest OS. Regrading the mailing thread[1], we have 4 possible combinations of these extensions in the device tree, the default hardware behavior for these possibilities are: 1) Neither Svade nor Svadu present in DT => It is technically unknown whether the platform uses Svade or Svadu. Supervisor may assume Svade to be present and enabled or it can discover based on mvendorid, marchid, and mimpid. 2) Only Svade present in DT => Supervisor must assume Svade to be always enabled. (Obvious) 3) Only Svadu present in DT => Supervisor must assume Svadu to be always enabled. (Obvious) 4) Both Svade and Svadu present in DT => Supervisor must assume Svadu turned-off at boot time. To use Svadu, supervisor must explicitly enable it using the SBI FWFT extension. The Svade extension is mandatory and the Svadu extension is optional in RVA23 profile. Platforms want to take the advantage of Svadu can choose 3. Those are aware of the profile can choose 4, and Linux won't get the benefit of svadu until the SBI FWFT extension is available. [1] https://lore.kernel.org/linux-kernel/20240527-e9845c06619bca5cd285098c@orel/T/#m29644eb88e241ec282df4ccd5199514e913b06ee --- v6: - reflect the platform's behavior by riscv_isa_extension_available() and update the the arch_has_hw_pte_young() in PATCH1 (Conor, Andrew) - update the dtbinding in PATCH2 (Alexandre, Andrew, Anup, Conor) - update the henvcfg condition in PATCH3 (Andrew) - check if Svade is allowed to disabled based on arch_has_hw_pte_young() in PATCH3 v5: - remove all Acked-by and Reviewed-by (Conor, Andrew) - add Svade support - update the arch_has_hw_pte_young() in PATCH1 - update the dtbinding in PATCH2 (Alexandre, Andrew) - check the availibility of Svadu for Guest/VM based on arch_has_hw_pte_young() in PATCH3 v4: - fix 32bit kernel build error in PATCH1 (Conor) - update the status of Svadu extension to ratified in PATCH2 - add the PATCH4 to suporrt SBI_FWFT_PTE_AD_HW_UPDATING for guest OS - update the PATCH1 and PATCH3 to integrate with FWFT extension - rebase PATCH5 on the lastest get-reg-list test (Andrew) v3: - fix the control bit name to ADUE in PATCH1 and PATCH3 - update get-reg-list in PATCH4 v2: - add Co-developed-by: in PATCH1 - use riscv_has_extension_unlikely() to runtime patch the branch in PATCH1 - update dt-binding Yong-Xuan Wang (4): RISC-V: Add Svade and Svadu Extensions Support dt-bindings: riscv: Add Svade and Svadu Entries RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test .../devicetree/bindings/riscv/extensions.yaml | 28 ++++++++++++++++ arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/pgtable.h | 13 +++++++- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++++++ arch/riscv/kvm/vcpu.c | 3 ++ arch/riscv/kvm/vcpu_onereg.c | 15 +++++++++ .../selftests/kvm/riscv/get-reg-list.c | 8 +++++ 10 files changed, 104 insertions(+), 1 deletion(-)