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Wed, 25 Sep 2024 06:15:57 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e06e1e09e2sm1479465a91.32.2024.09.25.06.15.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 25 Sep 2024 06:15:57 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, andy.chiu@sifive.com, guoren@kernel.org, christoph.muellner@vrull.eu, ajones@ventanamicro.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, lihangjing@bytedance.com, dengliang.1214@bytedance.com, xieyongji@bytedance.com, chaiwen.cc@bytedance.com, Xu Lu Subject: [PATCH v3 0/2] riscv: Idle thread using Zawrs extension Date: Wed, 25 Sep 2024 21:15:45 +0800 Message-Id: <20240925131547.42396-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_061603_306210_CA1E474F X-CRM114-Status: GOOD ( 10.44 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This is the third version of idle thread based on Zawrs extension. We noticed that Zawrs is supported in v6.11 now and rebased our code on it. Below is the original description. This patch series introduces a new implementation of idle thread using Zawrs extension. The Zawrs[0] extension introduces two new instructions named WRS.STO and WRS.NTO in RISC-V. When software registers a reservation set using LR instruction, a subsequent WRS.STO or WRS.NTO instruction will cause the hart to stall in a low-power state until a store happens to the reservation set or an interrupt becomes pending. The difference between these two instructions is that WRS.STO will terminate stall after an implementation-defined timeout while WRS.NTO won't. This patch series implements idle thread using WRS.NTO instruction. Besides, we found there is no need to send a real IPI to wake up an idle CPU. Instead, we write IPI information to the reservation set of an idle CPU to wake it up and let it handle IPI quickly, without going through tranditional interrupt handling routine. [0] https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Xu Lu (2): riscv: process: Introduce idle thread using Zawrs extension riscv: Use Zawrs to accelerate IPI to idle cpu arch/riscv/Kconfig | 10 +++ arch/riscv/include/asm/cpuidle.h | 11 +--- arch/riscv/include/asm/processor.h | 32 +++++++++ arch/riscv/include/asm/smp.h | 14 ++++ arch/riscv/kernel/cpu.c | 5 ++ arch/riscv/kernel/process.c | 102 ++++++++++++++++++++++++++++- arch/riscv/kernel/smp.c | 51 +++++++++++---- 7 files changed, 203 insertions(+), 22 deletions(-)