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AJvYcCXzcqhrGV8K8uMLeWbvtYP4SyfbTKMttBDBqvziZ4K99nj+Q6VzCVTOZryNwp5mtRGFuvmCO7uYpWPqjA==@lists.infradead.org X-Gm-Message-State: AOJu0Yyf3hxNBOQIRw3AtmOquDsFDC/dwJQmku6a3/ANifQQCLHjGQVx ycfr7HOS/+NB/XR6Vkyq3O36ilpsRSMf8TE1vvrYN2rrFdeMWCBI X-Google-Smtp-Source: AGHT+IGZ8LKVJxabPfVlar0jt5TJvCKTWMjDb3+j9MXgWzPHCHpqAnxCluoqe0yzk5w7hesyU6UCxw== X-Received: by 2002:a05:6a00:1397:b0:714:15ff:a2a4 with SMTP id d2e1a72fcca58-720b9c96d0emr2848144b3a.13.1730354969715; Wed, 30 Oct 2024 23:09:29 -0700 (PDT) Received: from localhost ([121.250.214.124]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc1b86b2sm572230b3a.37.2024.10.30.23.09.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 23:09:29 -0700 (PDT) From: Inochi Amaoto To: Chen Wang , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Inochi Amaoto , Guo Ren , Lad Prabhakar , Yangyu Chen , Anup Patel , Hal Feng , Geert Uytterhoeven Cc: Yixun Lan , Longbin Li , Inochi Amaoto , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI Date: Thu, 31 Oct 2024 14:08:56 +0800 Message-ID: <20241031060859.722258-1-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241030_230930_951625_A2A6E9D2 X-CRM114-Status: GOOD ( 11.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org New version of T-HEAD C920[1] implement a fully featured ACLINT device (This core is used by Sophgo SG2044). This ACLINT device provides a SSWI field to support fast S-mode IPI. This SSWI device is like the MSWI device in CLINT/ACLINT, but for S-mode. Add full support for T-HEAD C900 SSWI device. [1] https://www.xrvm.com/product/xuantie/C920 Changed from v1: 1. patch 2: use computed reg offset to avoid uncessary reg additions when setting/clearing irq. 2. patch 2: fix mulitple format issues and improve some comments. 3. patch 2: disable cpu irq when CPU is stopped. Changed from v2: 1. patch 2: add SXSTATUS.CLINTEE check for T-HEAD cores. 2. patch 2: add select GENERIC_IRQ_IPI_MUX in Kconfig Changed from v3: 1. patch 2: add SMP depends in Kconfig Changed from v4: 1. patch 1/2: update the description to mark the device is T-HEAD specific Inochi Amaoto (3): dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI irqchip: add T-HEAD C900 ACLINT SSWI driver riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers .../thead,c900-aclint-sswi.yaml | 58 ++++++ arch/riscv/configs/defconfig | 1 + drivers/irqchip/Kconfig | 12 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-thead-c900-aclint-sswi.c | 176 ++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 6 files changed, 249 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c --- 2.47.0