From patchwork Fri Dec 6 16:30:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13897455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B77CE77173 for ; Fri, 6 Dec 2024 16:39:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=1f9q1nIBXTuZ+DlIOeesNeATrswUN9HnqFSL3fgEP0Y=; b=kQ0nWG+0LxSWBi j0QyqTlUiMbs+rsKPHXHx+bTdxn81pno+uLROcgJI+aDw5u2F8oQBCcFaoVs8RHTEZp4vuDiPZX+C lZnup4BlXcoOhD7fJ4rG2HiGE7SY3DpzL4DDcjtTL3haT7J4KCEG2RDYoWoapp2tvT0LhfWnieb7k LZDW8kKCO3dpUbQ1XuEu/aW/kHLoXBEsaEqEIv+QKDWswnR0P8XdiysJQfL6TCC7U/vqQm1Yi45TY qTLi1fMjjVs9gf8obPU0giACUFnjyI9GoXjiOSvjR4mpXW2fDcuNbiJawZZqz2VEuykFgCzjQuQcF g+cR2rzP++BujgGKYyng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tJbMR-00000002CYz-2mxS; Fri, 06 Dec 2024 16:39:23 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tJbEU-00000002AIX-2jx0 for linux-riscv@lists.infradead.org; Fri, 06 Dec 2024 16:31:12 +0000 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3862a921123so731779f8f.3 for ; Fri, 06 Dec 2024 08:31:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733502668; x=1734107468; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=40IeoncDegwdvePviQ9Ac1q99emn7vMhde6cXPhiSAU=; b=Oz+8D5pHjd/SxODqn5J2Gp0qmfHFM8eYkwJOtWKa5nXCkwefdLUH/71+SG67yHqNM2 KxS4Qzdsq/E9AD2E0vIfRjyb4ctTkwh17amvWX9YapNmXN5zoxAZtximUiAPzivFxorc tfH6cCu7/qzOAEPRfv4x9E4wovffJWOXgMe83Ap71BsUFiaCsRKU5kdmYfr8oUEpGJGX QSkWiKelARSQe2MWQ3tgDYiILnuT3mMPFZLZhImxldupz9bTTJ2z0AWPzVp59Q7fAkGo 4Mi16VYFutayMk2HygPjwpmCKtfHN6RCaHObNPZV7+qQ9XW07cfYMvM54XbJ80nn5MoP UMww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733502668; x=1734107468; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=40IeoncDegwdvePviQ9Ac1q99emn7vMhde6cXPhiSAU=; b=X1F9r2pVXALJdXv8Fs9SU4gaL1sWm5j0LV4uui0PzYphFv+iIkn45cqkfIQBoCxd/a eVQ3lK68jSjIowy+DiGdX1N44BqokFKeLE37M6dsrxd1UHmVkg2SocDsJQqEkf7eFF1c /xzc9JTl9eZOWei3oKflYVmcbiiLMkZAkkMd9AEAQOlPeQgoNuEiGByb2stOdPzU3w7b cfvFIuzWqGMe3GDb2eLufqLlS1RjecBg98eBglGjSBF+v57EhVIWXox/WS8RoqR0H+hu FEHXzU3CREvkh4Ml6IIjpFbVAmN0Mn2Vbhsk3WkOv9aAPBMYGNrR8gpcirXCvFxj1T9y 24Uw== X-Forwarded-Encrypted: i=1; AJvYcCXsMXV7Ani+64ShpCWpkLfNg+ioF46XIrVgjg+DGrtwC07Vwe7xdHmvkUKOX3NrA0Y8QhqexQKk5V0k4A==@lists.infradead.org X-Gm-Message-State: AOJu0YxISEVu/Zkg1pHyI80C5AE5x+Fqji/amNqqR/vxO7kcN1BOM408 mxK5f2RD00t+vZpEWqI49fy0N3Jc12hQ+zJ1PU2pN3gXJe4MnOAGXHt5x0rDUhk= X-Gm-Gg: ASbGncsC9C1MYW3Wz2RTWVRvpOvqB8SUZ9RZ9tWoZ54oS4uol8jdnY0zTFBtyrrQfZv cO8ddnCnlQOsUlRamkvULiIzdqtfr1G+yfSezVexEoQ1Dvn57sm32S1fL0wTxmhLRlWBkv3v+B6 3O/QHRY5apsNyq8JrFWZGOmI9RjA3J+ZRJbwYXJvgmiw0cgwEa7mqs79QGEjYM4pZTuiL2vLECP oSjHlIuvCTNQ2VJCkx3iMadp3iMhYs3o9UI77ydeB6x1GI3nsI= X-Google-Smtp-Source: AGHT+IHAkbc/dcGz/MjNU6vQq8UGceABhupZgIW1uIKLdzsf3QUJS33oSh5p4cBX6H9+RneNbzUK4A== X-Received: by 2002:a5d:59a3:0:b0:385:dffb:4d66 with SMTP id ffacd0b85a97d-3862b36a491mr2894353f8f.17.1733502668076; Fri, 06 Dec 2024 08:31:08 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3862f02f5c3sm1151942f8f.65.2024.12.06.08.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2024 08:31:07 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Himanshu Chauhan , Anup Patel , Xu Lu , Atish Patra Subject: [PATCH v3 0/4] riscv: add support for SBI Supervisor Software Events Date: Fri, 6 Dec 2024 17:30:56 +0100 Message-ID: <20241206163102.843505-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241206_083110_951426_B61D2336 X-CRM114-Status: GOOD ( 21.11 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The SBI Supervisor Software Events (SSE) extensions provides a mechanism to inject software events from an SBI implementation to supervisor software such that it preempts all other supervisor level traps and interrupts. This specification is introduced by the SBI v3.0 specification[1]. Various events are defined and can be send asynchronously to supervisor software (RAS, PMU, DEBUG, Asynchronous page fault) from SBI as well as platform specific events. Events can be either local (per-hart) or global. Events can be nested on top of each other based on priority and can interrupt the kernel at any time. First patch adds the SSE definitions. Second one adds support for SSE at arch level (entry code and stack allocations) and third one at driver level. Finally, the last patch add support for SSE events in the SBI PMU driver. Additional testing for that part is highly welcomed since there are a lot of possible path that needs to be exercised. Amongst the specific points that needs to be handle is the interruption at any point of the kernel execution and more specifically at the beggining of exception handling. Due to the fact that the exception entry implementation uses the SCRATCH CSR as both the current task struct and as the temporary register to switch the stack and save register, it is difficult to reliably get the current task struct if we get interrupted at this specific moment (ie, it might contain 0, the task pointer or tp). A fixup-like mechanism is not possible due to the nested nature of SSE which makes it really hard to obtain the original interruption site. In order to retrieve the task in a reliable maneer, add an additional __sse_entry_task per_cpu array which stores the current task. Ideally, we would need to modify the way we retrieve/store the current task in exception handling so that it does not depend on the place where it's interrupted. Contrary to pseudo NMI [2], SSE does not modifies the way interrupts are handled and does not adds any overhead to existing code. Moreover, it provides "true" NMI-like interrupts which can interrupt the kernel at any time (even in exception handling). This is particularly crucial for RAS errors which needs to be handled as fast as possible to avoid any fault propagation. OpenSBI SSE support is already upstream. Link: https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/vv3.0-rc2/riscv-sbi.pdf [1] --- Changes in v3: - Split arch/driver support - Fix potential register failure reporting - Set a few pr_err as pr_debug - Allow CONFIG_RISCV_SSE to be disabled - Fix build without CONFIG_RISCV_SSE - Remove fixup-like mechanism and use a per-cpu array - Fixed SSCRATCH being corrupted when interrupting the kernel in early exception path. - Split SSE assembly from entry.S - Add Himanchu SSE mask/unmask and runtime PM support. - Disable user memory access/floating point/vector in SSE handler - Rebased on master v2: https://lore.kernel.org/linux-riscv/20240112111720.2975069-1-cleger@rivosinc.com/ Changes in v2: - Implemented specification v2 - Fix various error handling cases - Added shadow stack support v1: https://lore.kernel.org/linux-riscv/20231026143122.279437-1-cleger@rivosinc.com/ Clément Léger (4): riscv: add SBI SSE extension definitions riscv: add support for SBI Supervisor Software Events extension drivers: firmware: add riscv SSE support perf: RISC-V: add support for SSE event MAINTAINERS | 14 + arch/riscv/include/asm/asm.h | 14 +- arch/riscv/include/asm/sbi.h | 62 +++ arch/riscv/include/asm/scs.h | 7 + arch/riscv/include/asm/sse.h | 38 ++ arch/riscv/include/asm/switch_to.h | 14 + arch/riscv/include/asm/thread_info.h | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 12 + arch/riscv/kernel/sse.c | 134 ++++++ arch/riscv/kernel/sse_entry.S | 171 +++++++ drivers/firmware/Kconfig | 1 + drivers/firmware/Makefile | 1 + drivers/firmware/riscv/Kconfig | 15 + drivers/firmware/riscv/Makefile | 3 + drivers/firmware/riscv/riscv_sse.c | 691 +++++++++++++++++++++++++++ drivers/perf/riscv_pmu_sbi.c | 51 +- include/linux/riscv_sse.h | 56 +++ 18 files changed, 1273 insertions(+), 13 deletions(-) create mode 100644 arch/riscv/include/asm/sse.h create mode 100644 arch/riscv/kernel/sse.c create mode 100644 arch/riscv/kernel/sse_entry.S create mode 100644 drivers/firmware/riscv/Kconfig create mode 100644 drivers/firmware/riscv/Makefile create mode 100644 drivers/firmware/riscv/riscv_sse.c create mode 100644 include/linux/riscv_sse.h