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[89.144.193.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390db110dfsm97904245e9.36.2025.02.07.08.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:19:41 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Date: Fri, 7 Feb 2025 17:19:40 +0100 Message-ID: <20250207161939.46139-11-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250207_081944_464002_8CB132EA X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The first six patches of this series are fixes and cleanups of the unaligned access speed probing code. The next two patches introduce support to skip probing by matching vendor/arch/imp ids and checking a table for the access speed type. The last patch applies the new skip support to Ventana harts. (I'd be happy to split the fixes from the new skip support if we want to discuss the skip support independently, but I want to base on the fixes and I'm not sure if patchwork supports Based-on: $MESSAGE_ID/$LORE_URL or not at the moment, so I'm just posting together for now in order to be able to check for my patchwork green lights!) Thanks, drew Andrew Jones (9): riscv: Annotate unaligned access init functions riscv: Fix riscv_online_cpu_vec riscv: Fix check_unaligned_access_all_cpus riscv: Change check_unaligned_access_speed_all_cpus to void riscv: Fix set up of cpu hotplug callbacks riscv: Fix set up of vector cpu hotplug callback riscv: Prepare for unaligned access type table lookups riscv: Implement check_unaligned_access_table riscv: Add Ventana unaligned access table entries arch/riscv/include/asm/cpufeature.h | 4 +- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/traps_misaligned.c | 14 +- arch/riscv/kernel/unaligned_access_speed.c | 278 ++++++++++++++------- 4 files changed, 200 insertions(+), 97 deletions(-)