From patchwork Wed Jul 19 19:33:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tomasz Jeznach X-Patchwork-Id: 13319425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE2A4C001DC for ; Wed, 19 Jul 2023 19:34:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=B3m7YakZIXnia45VBQI5AEiTwExjGpCut4pXHSbsTeQ=; b=E9VeBIsbXwvtc2 Chw6G6jeazMeb70fipmRM7v3s4lRL/y6+iTlH90hHsiowBBlqhAOSv0+xEy+wxbALNYr0XExJ2DmN v6aBYQWKZYKtliaf39RoaHRI8e9eXofyz1ioV8zrqhf0/ETu0sjCNtm9wnKTS/8dSybB3nMKilWdC gexHyQhzEQJbdYRe98t+5QJEVVZ10BQKhaKvBH2HVPC+mzTPvbFUDEkIHBMLKJdJMY0DQzb4n995C TtAk/ui4QB40i3bbr7hOByhst0wyEr1PYOjxWxZN4SJ9MCWSUEgY1klfNhR31DseBh9Us26obHxGp fpSpBCJhTuPkBW+JI0JA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMCwP-008h4I-00; Wed, 19 Jul 2023 19:34:29 +0000 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMCwL-008h2I-1R for linux-riscv@lists.infradead.org; Wed, 19 Jul 2023 19:34:27 +0000 Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-3a40b756eb0so27521b6e.2 for ; Wed, 19 Jul 2023 12:34:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1689795264; x=1690400064; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=898LnY9cJ7dwalJq3UYz/mDCfelRokl75v2pZe5QKSg=; b=tMmyEGaoPTP9a//tyRq8ynyPcoPNJdciVKPWijs/mHL/jvUK6t+mofl3RDIRUrqhHH 6A/Bgjz2ykqJKTI4hg3/XFEN7w4lXR5J/KP1u8uT/YTr6Z+6jXCc0FUOD+0HnKbrdq0h j/v+Lliv5+aYmrGP/O3nneO/w19BZwcbfi2o8LKoDxmKmwcbs3q02CZjSMkjuIizzTqx kBe5/+rvpVf3k8KLJ8u+xQ6vhFwDqSNyCkQdHz33+jKYYJ53toPXjTQJUP638HtzYjtG /JWV9aAZdC4MEkhGhyqQfUsKtc8nGwEeNKSA5xeoRVY+a3ZhjczWtNCXH+tJRdEwAUq2 u8yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689795264; x=1690400064; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=898LnY9cJ7dwalJq3UYz/mDCfelRokl75v2pZe5QKSg=; b=BCy9eHKP7gFY9kwTAUZz2cPf/6jxa/VzEAB2hGbKIiVhl/0KSfSEuCndkDN3G3J+lE o+wadqPg33E/DpC0pkHZJj68+whyqCwRHDbYQON5idS6YPDbnCDe/LmXf5GWg5q6FBLZ KiRWBeWRGqCre1ztkj9FK+PmmdPtv56QYv/mWtgaReX49HsplpPLybei+hGZ/RN3PyUF UfuJ7lo3zPUysELnqhN+eR9LS4I/0dkMcHeom477bIv3udwzEoaQWW76DGgNhVJKOlws KiorvxQ3lXniiLlPIeZXGP+MkzPpg67FRlNVFabRCsoTpullq4cz8Oy5gcPd9z1sH8pi BUlg== X-Gm-Message-State: ABy/qLbZw10jzmdRW4wPQnMk5CPF1XgUdrIXSGynLzitZ/pa8B8w/4VP WZYdrL01w+gdvjkefv/aBx09gg== X-Google-Smtp-Source: APBJJlFS8kYmxrMQdI6vVbg8tjqWVgqnH6tvKbzas7Xx07kyU9Ed8nJU/Yakj0txh6GAxjHkYRUqBw== X-Received: by 2002:a05:6808:19a5:b0:3a4:6cc2:893e with SMTP id bj37-20020a05680819a500b003a46cc2893emr488344oib.56.1689795263740; Wed, 19 Jul 2023 12:34:23 -0700 (PDT) Received: from tjeznach.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id 23-20020a17090a031700b00264040322desm1591053pje.40.2023.07.19.12.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 12:34:23 -0700 (PDT) From: Tomasz Jeznach To: Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley Subject: [PATCH 00/13] Linux RISC-V IOMMU Support Date: Wed, 19 Jul 2023 12:33:44 -0700 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230719_123425_726666_2A84DAD7 X-CRM114-Status: GOOD ( 16.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Albert Ou , Tomasz Jeznach , linux@rivosinc.com, linux-kernel@vger.kernel.org, Sebastien Boeuf , iommu@lists.linux.dev, Palmer Dabbelt , Nick Kossifidis , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The RISC-V IOMMU specification is now ratified as-per the RISC-V international process [1]. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf At a high-level, the RISC-V IOMMU specification defines: 1) Memory-mapped programming interface - Mandatory and optional registers layout and description. - Software guidelines for device initialization and capabilities discovery. 2) In-memory queue interface - A command-queue used by software to queue commands to the IOMMU. - A fault/event queue used to bring faults and events to software’s attention. - A page-request queue used to report “Page Request” messages received from PCIe devices. - Message-signalled and wire-signaled interrupt mechanism. 3) In-memory data structures - Device-context: used to associate a device with an address space and to hold other per-device parameters used by the IOMMU to perform address translations. - Process-contexts: used to associate a different virtual address space based on device provided process identification number. - MSI page table configuration used to direct an MSI to a guest interrupt file in an IMSIC. The MSI page table formats are defined by the Advanced Interrupt Architecture specification [2]. This series introduces complete single-level translation support, including shared virtual address (SVA), ATS/PRI interfaces in the kernel driver. Patches adding MSI identity remapping and G-Stage translation (GPA to SPA) are added only to excercise hardware interfaces, to be complemented with AIA/KVM bindings in follow-up series. This series is a logical regrouping of series of incremental patches based on RISC-V International IOMMU Task Group discussions and specification development process. Original series can be found at the maintainer's repository branch [3]. These patches can also be found in the riscv_iommu_v1 branch at: https://github.com/tjeznach/linux/tree/riscv_iommu_v1 To test this series, use QEMU/OpenSBI with RISC-V IOMMU implementation available in the riscv_iommu_v1 branch at: https://github.com/tjeznach/qemu/tree/riscv_iommu_v1 References: [1] - https://wiki.riscv.org/display/HOME/Specification+Status [2] - https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf [3] - https://github.com/tjeznach/qemu/tree/tjeznach/riscv-iommu-20230719 Anup Patel (1): dt-bindings: Add RISC-V IOMMU bindings Tomasz Jeznach (10): RISC-V: drivers/iommu: Add RISC-V IOMMU - Ziommu support. RISC-V: arch/riscv/config: enable RISC-V IOMMU support MAINTAINERS: Add myself for RISC-V IOMMU driver RISC-V: drivers/iommu/riscv: Add sysfs interface RISC-V: drivers/iommu/riscv: Add command, fault, page-req queues RISC-V: drivers/iommu/riscv: Add device context support RISC-V: drivers/iommu/riscv: Add page table support RISC-V: drivers/iommu/riscv: Add SVA with PASID/ATS/PRI support. RISC-V: drivers/iommu/riscv: Add MSI identity remapping RISC-V: drivers/iommu/riscv: Add G-Stage translation support .../bindings/iommu/riscv,iommu.yaml | 146 ++ MAINTAINERS | 7 + arch/riscv/configs/defconfig | 1 + drivers/iommu/Kconfig | 1 + drivers/iommu/Makefile | 2 +- drivers/iommu/io-pgtable.c | 3 + drivers/iommu/riscv/Kconfig | 22 + drivers/iommu/riscv/Makefile | 1 + drivers/iommu/riscv/io_pgtable.c | 266 ++ drivers/iommu/riscv/iommu-bits.h | 704 ++++++ drivers/iommu/riscv/iommu-pci.c | 206 ++ drivers/iommu/riscv/iommu-platform.c | 160 ++ drivers/iommu/riscv/iommu-sysfs.c | 183 ++ drivers/iommu/riscv/iommu.c | 2130 +++++++++++++++++ drivers/iommu/riscv/iommu.h | 165 ++ include/linux/io-pgtable.h | 2 + 16 files changed, 3998 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml create mode 100644 drivers/iommu/riscv/Kconfig create mode 100644 drivers/iommu/riscv/Makefile create mode 100644 drivers/iommu/riscv/io_pgtable.c create mode 100644 drivers/iommu/riscv/iommu-bits.h create mode 100644 drivers/iommu/riscv/iommu-pci.c create mode 100644 drivers/iommu/riscv/iommu-platform.c create mode 100644 drivers/iommu/riscv/iommu-sysfs.c create mode 100644 drivers/iommu/riscv/iommu.c create mode 100644 drivers/iommu/riscv/iommu.h