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The RISC-V IOMMU specification, which this series is based on, is ratified and available at GitHub/riscv-non-isa [1]. At a high level, the RISC-V IOMMU specification defines: 1) Data structures: - Device-context: Associates devices with address spaces and holds per-device parameters for address translations. - Process-contexts: Associates different virtual address spaces based on device-provided process identification numbers. - MSI page table configuration used to direct an MSI to a guest interrupt file in an IMSIC. 2) In-memory queue interface: - Command-queue for issuing commands to the IOMMU. - Fault/event queue for reporting faults and events. - Page-request queue for reporting "Page Request" messages received from PCIe devices. - Message-signaled and wire-signaled interrupt mechanisms. 3) Memory-mapped programming interface: - Mandatory and optional register layout and description. - Software guidelines for device initialization and capabilities discovery. This series introduces RISC-V IOMMU hardware initialization and complete single-stage translation with paging domain support. The patches are organized as follows: Patch 1: Introduces minimal required device tree bindings for the driver. Patch 2: Defines RISC-V IOMMU data structures, hardware programming interface registers layout, and minimal initialization code for enabling global pass-through for all connected masters. Patch 3: Implements the device driver for PCIe implementation of RISC-V IOMMU architected hardware. Patch 4: Introduces IOMMU interfaces to the kernel subsystem. Patch 5: Implements device directory management with discovery sequences for I/O mapped or in-memory device directory table location, hardware capabilities discovery, and device to domain attach implementation. Patch 6: Implements command and fault queue, and introduces directory cache invalidation sequences. Patch 7: Implements paging domain, using highest page-table mode advertised by the hardware. This series enables only 4K mappings; complete support for large page mappings will be introduced in follow-up patch series. Follow-up patch series, providing large page support and updated walk cache management based on the revised specification, and complete ATS/PRI/SVA support, will be posted to GitHub [2]. Changes from v6: - rebase on v6.10-rc2 - editorial changes in iommu-bits.h addressing Drew's comments - fix IOVA length check in riscv_iommu_iotlb_inval() Best regards, Tomasz Jeznach [1] link: https://github.com/riscv-non-isa/riscv-iommu [2] link: https://github.com/tjeznach/linux v6 link: https://lore.kernel.org/linux-iommu/cover.1716578450.git.tjeznach@rivosinc.com/ v5 link: https://lore.kernel.org/linux-iommu/cover.1715708679.git.tjeznach@rivosinc.com/ v4 link: https://lore.kernel.org/linux-iommu/cover.1714752293.git.tjeznach@rivosinc.com/ v3 link: https://lore.kernel.org/linux-iommu/cover.1714494653.git.tjeznach@rivosinc.com/ v2 link: https://lore.kernel.org/linux-iommu/cover.1713456597.git.tjeznach@rivosinc.com/ v1 link: https://lore.kernel.org/linux-iommu/cover.1689792825.git.tjeznach@rivosinc.com/ Tomasz Jeznach (7): dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU iommu/riscv: Add RISC-V IOMMU platform device driver iommu/riscv: Add RISC-V IOMMU PCIe device driver iommu/riscv: Enable IOMMU registration and device probe. iommu/riscv: Device directory management. iommu/riscv: Command and fault queue support iommu/riscv: Paging domain support .../bindings/iommu/riscv,iommu.yaml | 147 ++ MAINTAINERS | 8 + drivers/iommu/Kconfig | 1 + drivers/iommu/Makefile | 2 +- drivers/iommu/riscv/Kconfig | 20 + drivers/iommu/riscv/Makefile | 3 + drivers/iommu/riscv/iommu-bits.h | 784 ++++++++ drivers/iommu/riscv/iommu-pci.c | 119 ++ drivers/iommu/riscv/iommu-platform.c | 92 + drivers/iommu/riscv/iommu.c | 1677 +++++++++++++++++ drivers/iommu/riscv/iommu.h | 88 + 11 files changed, 2940 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml create mode 100644 drivers/iommu/riscv/Kconfig create mode 100644 drivers/iommu/riscv/Makefile create mode 100644 drivers/iommu/riscv/iommu-bits.h create mode 100644 drivers/iommu/riscv/iommu-pci.c create mode 100644 drivers/iommu/riscv/iommu-platform.c create mode 100644 drivers/iommu/riscv/iommu.c create mode 100644 drivers/iommu/riscv/iommu.h base-commit: c3f38fa61af77b49866b006939479069cd451173