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For gemgxlpll/cltxpll clocks in fu540/fu740, the reset pins also have to be relased for the device to function properly. This was missing in Linux. The board (Sifive Unmatched/Unleashed) happened to work because previous boot stage (u-boot) usually already enables the clocks when trying to boot from PXE/network, and the release_reset logic is present in u-boot. When booting directly from firmware (OpenSBI) or when u-boot isn't configured with networking enabled, the board will hang when cadence/macb driver starts initializing the device. Fix that by taking the same logic in u-boot and apply to linux. Bo Gan (3): dt-bindings: reset: sifive: add fu540/fu740 reset indexes riscv: dts: sifive: fu740: Use reset index from header clk: sifive: prci: Add release_reset hooks for gemgxlpll/cltxpll arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 3 +- drivers/clk/sifive/fu540-prci.h | 16 ++++++++++ drivers/clk/sifive/fu740-prci.h | 31 +++++++++++++++++++ drivers/clk/sifive/sifive-prci.c | 23 ++++++++++++++ drivers/clk/sifive/sifive-prci.h | 8 +++++ include/dt-bindings/reset/sifive-fu540-prci.h | 19 ++++++++++++ include/dt-bindings/reset/sifive-fu740-prci.h | 19 ++++++++++++ 7 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h