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AJvYcCWYywzcPj1pEoGc1fyJo4ABTjT+r3N4rlPrnkJZpFbz4nCwEFctF5jr9reWMCgU0xgVCMoR1tGrcqdThg==@lists.infradead.org X-Gm-Message-State: AOJu0YxNsVwkuqtYbM3Az04ROoJvGxUSQJIo0OoTm3IG30h7qLMxMe9C uNRfvc9EmUKxlHHTquLUqxZBTu/dd0VGrmyYPIgozvwUZlE4CUqQ X-Google-Smtp-Source: AGHT+IF4wa34kPK0D2j4YiwZgM0PWB0bX/gx1QEPBQEvPCwAAOOwKKwE2xLSY6u7rz/iBj7/3S5myQ== X-Received: by 2002:a05:6830:6c10:b0:710:f3cb:5b9d with SMTP id 46e09a7af769-71a1c298638mr9014021a34.24.1731304767775; Sun, 10 Nov 2024 21:59:27 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71a107ebea1sm2125534a34.14.2024.11.10.21.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 21:59:26 -0800 (PST) From: Chen Wang To: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC Date: Mon, 11 Nov 2024 13:59:17 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241110_215928_960958_7F9B31C7 X-CRM114-Status: GOOD ( 11.83 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Chen Wang Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode. SG2042 PCIe controller supports two ways to report MSI: Method A, the PICe controller implements an MSI interrupt controller inside, and connect to PLIC upward through one interrupt line. Provides memory-mapped msi address, and by programming the upper 32 bits of the address to zero, it can be compatible with old pcie devices that only support 32-bit msi address. Method B, the PICe controller connects to PLIC upward through an independent MSI controller "sophgo,sg2042-msi" on the SOC. The MSI controller provides multiple(up to 32) interrupt sources to PLIC. Compared with the first method, the advantage is that the interrupt source is expanded, but because for SG2042, the msi address provided by the MSI controller is fixed and only supports 64-bit address(> 2^32), it is not compatible with old pcie devices that only support 32-bit msi address. This patchset depends on another patchset for the SG2042 MSI controller[msi]. If you need to test the DTS part, you need to apply the corresponding patchset. Link: https://lore.kernel.org/linux-riscv/cover.1731296803.git.unicorn_wang@outlook.com/ [msi] Thanks, Chen Chen Wang (5): dt-bindings: pci: Add Sophgo SG2042 PCIe host PCI: sg2042: Add Sophgo SG2042 PCIe driver dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible riscv: sophgo: dts: add pcie controllers for SG2042 riscv: sophgo: dts: enable pcie for PioneerBox .../devicetree/bindings/mfd/syscon.yaml | 2 + .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 88 +++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 82 +++ drivers/pci/controller/cadence/Kconfig | 11 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pcie-sg2042.c | 611 ++++++++++++++++++ 7 files changed, 807 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c base-commit: 2d5404caa8c7bb5c4e0435f94b28834ae5456623