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Thu, 20 Feb 2025 21:49:44 -0800 (PST) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH v4 0/3] irqchip: Add Sophgo SG2042 MSI controller Date: Fri, 21 Feb 2025 13:49:29 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_214947_300797_A61C9C52 X-CRM114-Status: GOOD ( 10.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Chen Wang This controller is on the Sophgo SG2042 SoC to transform interrupts from PCIe MSI to PLIC interrupts. Thanks, Chen --- Changes in v4: The patch series is based on v6.14-rc1. Fixed following issues as per comments from Inochi Amaoto, Rob Herring, thanks. - bindings: - Update sequence of "reg-names". - Remove reference to/schemas/interrupts.yaml - Add "#msi-cells". - Improve driver code: - Use fwnode_* instead of of_*. - Some other coding style improvements. Changes in v3: The patch series is based on v6.13-rc7. You can simply review or test the patches at the link [3]. Fixed following issues as per comments from Krzysztof Kozlowski, Samuel Holland, Christophe JAILLET, Inochi Amaoto, thanks. - bindings: use reg for doorbell, fixed wrong usage of additionalProperties and misc. - Improve driver code: - Fixed potentional memory leak issues. - Fixed some build warnings reported by test robot. - Optimize and simplify the code when allocating hwirq. - Use DECLARE_BITMAP instead of kzalloc. - Some other coding style improvements. Changes in v2: The patch series is based on v6.13-rc2. You can simply review or test the patches at the link [2]. Fixed following issues as per comments from Rob Herring, Thomas Gleixner, thanks. - Improve driver binding description, use msi-ranges instread. - Improve driver code: - Improve coding style. - Fixed bug that possible memory leak of bitmap when sg2042_msi_init_domains returns error. - Use guard(mutex). - Use the MSI parent model. Changes in v1: The patch series is based on v6.12-rc7. You can simply review or test the patches at the link [1]. Link: https://lore.kernel.org/linux-riscv/cover.1731296803.git.unicorn_wang@outlook.com/ [1] Link: https://lore.kernel.org/linux-riscv/cover.1733726057.git.unicorn_wang@outlook.com/ [2] Link: https://lore.kernel.org/linux-riscv/cover.1736921549.git.unicorn_wang@outlook.com/ [3] --- Chen Wang (3): dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI irqchip: Add the Sophgo SG2042 MSI interrupt controller riscv: sophgo: dts: add msi controller for SG2042 .../sophgo,sg2042-msi.yaml | 61 ++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 10 + drivers/irqchip/Kconfig | 12 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sg2042-msi.c | 264 ++++++++++++++++++ 5 files changed, 348 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml create mode 100644 drivers/irqchip/irq-sg2042-msi.c base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b