Show patches with: State = Action Required       |   8851 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,3/5] RISC-V: Define fixmap bindings for generic early ioremap support Add UEFI support for RISC-V 1 - - --- 2020-02-27 Atish Patra New
[v1,2/5] include: pe.h: Add RISC-V related PE definition Add UEFI support for RISC-V - 1 - --- 2020-02-27 Atish Patra New
[v1,1/5] efi: Move arm-stub to a common file Add UEFI support for RISC-V - - - --- 2020-02-27 Atish Patra New
[3/3] RISC-V: Stop using LOCAL for the uaccess fixups [1/3] RISC-V: Stop relying on GCC's register allocator's hueristics - - - --- 2020-02-27 Palmer Dabbelt New
[2/3] RISC-V: Inline the assembly register save/restore macros [1/3] RISC-V: Stop relying on GCC's register allocator's hueristics - 1 - --- 2020-02-27 Palmer Dabbelt New
[1/3] RISC-V: Stop relying on GCC's register allocator's hueristics [1/3] RISC-V: Stop relying on GCC's register allocator's hueristics - - - --- 2020-02-27 Palmer Dabbelt New
mm/debug: Add tests validating arch page table helpers for core features mm/debug: Add tests validating arch page table helpers for core features - - - --- 2020-02-27 Anshuman Khandual New
[v10,12/12] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,11/12] RISC-V: Support cpu hotplug Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,10/12] RISC-V: Add supported for ordered booting method using HSM Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,09/12] RISC-V: Add SBI HSM extension definitions Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,08/12] RISC-V: Export SBI error to linux error mapping function Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,07/12] RISC-V: Add cpu_ops and modify default booting method Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,06/12] RISC-V: Move relocate and few other functions out of __init Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,05/12] RISC-V: Implement new SBI v0.2 extensions Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,04/12] RISC-V: Introduce a new config for SBI v0.1 Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-26 Atish Patra New
[v10,03/12] RISC-V: Add SBI v0.2 extension definitions Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-26 Atish Patra New
[v10,02/12] RISC-V: Add basic support for SBI v0.2 Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-26 Atish Patra New
[v10,01/12] RISC-V: Mark existing SBI as 0.1 SBI. Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-26 Atish Patra New
[RFC,5/5] RISC-V: Add EFI stub support. Add UEFI support for RISC-V - - - --- 2020-02-26 Atish Patra New
[RFC,4/5] RISC-V: Add PE/COFF header for EFI stub Add UEFI support for RISC-V - - - --- 2020-02-26 Atish Patra New
[RFC,3/5] RISC-V: Define fixmap bindings for generic early ioremap support Add UEFI support for RISC-V 1 - - --- 2020-02-26 Atish Patra New
[RFC,2/5] include: pe.h: Add RISC-V related PE definition Add UEFI support for RISC-V - 1 - --- 2020-02-26 Atish Patra New
[RFC,1/5] efi: Move arm-stub to a common file Add UEFI support for RISC-V - - - --- 2020-02-26 Atish Patra New
[GIT,PULL] RISC-V Fixes for 5.6-rc4 [GIT,PULL] RISC-V Fixes for 5.6-rc4 - - - --- 2020-02-25 Palmer Dabbelt New
RISC-V: Move all address space definition macros to one place RISC-V: Move all address space definition macros to one place - 1 - --- 2020-02-24 Atish Patra New
[v2] irqchip/sifive-plic: Add support for multiple PLICs [v2] irqchip/sifive-plic: Add support for multiple PLICs - 1 - --- 2020-02-21 Atish Patra New
[V2,2/2] riscv: Change code model of module to medany to improve data accessing solve static percpu symbol issue in module and refine code model of module - - - --- 2020-02-21 Vincent Chen New
[V2,1/2] riscv: avoid the PIC offset of static percpu data in module beyond 2G limits solve static percpu symbol issue in module and refine code model of module - - 2 --- 2020-02-21 Vincent Chen New
[v9,12/12] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,11/12] RISC-V: Support cpu hotplug Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,10/12] RISC-V: Add supported for ordered booting method using HSM Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,09/12] RISC-V: Add SBI HSM extension definitions Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,08/12] RISC-V: Export SBI error to linux error mapping function Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,07/12] RISC-V: Add cpu_ops and modify default booting method Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,06/12] RISC-V: Move relocate and few other functions out of __init Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,05/12] RISC-V: Implement new SBI v0.2 extensions Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,04/12] RISC-V: Introduce a new config for SBI v0.1 Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-21 Atish Patra New
[v9,03/12] RISC-V: Add SBI v0.2 extension definitions Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-21 Atish Patra New
[v9,02/12] RISC-V: Add basic support for SBI v0.2 Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-21 Atish Patra New
[v9,01/12] RISC-V: Mark existing SBI as 0.1 SBI. Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-21 Atish Patra New
riscv: Use p*d_leaf macros to define p*d_huge riscv: Use p*d_leaf macros to define p*d_huge - 1 - --- 2020-02-20 Alexandre Ghiti New
[v5,2/2] riscv: Add support to determine no. of L2 cache way enabled cacheinfo support to read no. of L2 cache ways enabled - 1 - --- 2020-02-20 Yash Shah New
[v5,1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure cacheinfo support to read no. of L2 cache ways enabled - 1 - --- 2020-02-20 Yash Shah New
[v3,bpf-next] RV32G eBPF JIT [v3,bpf-next] RV32G eBPF JIT - - - --- 2020-02-20 Luke Nelson New
[v3,4/4] RISC-V: Remove do_IRQ() function New RISC-V Local Interrupt Controller Driver - - - --- 2020-02-19 Anup Patel New
[v3,3/4] clocksource: timer-riscv: Make timer interrupt as a per-CPU interrupt New RISC-V Local Interrupt Controller Driver - - - --- 2020-02-19 Anup Patel New
[v3,2/4] irqchip: RISC-V Per-HART Local Interrupt Controller Driver New RISC-V Local Interrupt Controller Driver - - - --- 2020-02-19 Anup Patel New
[v3,1/4] RISC-V: self-contained IPI handling routine New RISC-V Local Interrupt Controller Driver - - - --- 2020-02-19 Anup Patel New
[2/2] riscv: Change code model of module to medany to improve data accessing solve static percpu symbol issue in module and refine code model of module - - - --- 2020-02-19 Vincent Chen New
[1/2] riscv: avoid the PIC offset of static percpu data in module beyond 2G limits solve static percpu symbol issue in module and refine code model of module - - 2 --- 2020-02-19 Vincent Chen New
documentation: vm: Advertise support for pte_special in riscv documentation: vm: Advertise support for pte_special in riscv - - - --- 2020-02-19 Alexandre Ghiti New
riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file - 1 - --- 2020-02-19 Yash Shah New
RISC-V: Stop putting .sbss in .sdata RISC-V: Stop putting .sbss in .sdata - - 1 --- 2020-02-18 Palmer Dabbelt New
[8/8] riscv: add two hook functions of ftrace Support strict kernel memory permissions for security - - - --- 2020-02-17 Zong Li New
[7/8] riscv: add DEBUG_WX support Support strict kernel memory permissions for security - - - --- 2020-02-17 Zong Li New
[6/8] riscv: add STRICT_KERNEL_RWX support Support strict kernel memory permissions for security - - - --- 2020-02-17 Zong Li New
[5/8] riscv: add alignment for text, rodata and data sections Support strict kernel memory permissions for security - 1 - --- 2020-02-17 Zong Li New
[4/8] riscv: move exception table immediately after RO_DATA Support strict kernel memory permissions for security - - - --- 2020-02-17 Zong Li New
[3/8] riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support Support strict kernel memory permissions for security - 1 - --- 2020-02-17 Zong Li New
[2/8] riscv: add ARCH_HAS_SET_DIRECT_MAP support Support strict kernel memory permissions for security - 1 - --- 2020-02-17 Zong Li New
[1/8] riscv: add ARCH_HAS_SET_MEMORY support Support strict kernel memory permissions for security - 1 - --- 2020-02-17 Zong Li New
riscv: Fix range looking for kernel image memblock riscv: Fix range looking for kernel image memblock - 2 - --- 2020-02-17 Alexandre Ghiti New
[V14] mm/debug: Add tests validating architecture page table helpers [V14] mm/debug: Add tests validating architecture page table helpers - 1 2 --- 2020-02-17 Anshuman Khandual New
kbuild: use KBUILD_DEFCONFIG as the fallback for DEFCONFIG_LIST kbuild: use KBUILD_DEFCONFIG as the fallback for DEFCONFIG_LIST - - - --- 2020-02-16 Masahiro Yamada New
[v2,3/3] riscv: Fix crash when flushing executable ioremap regions riscv: mem= support, ioremap exec fix - - - --- 2020-02-15 Jan Kiszka New
[v2,2/3] riscv: End kernel region search in setup_bootmem earlier riscv: mem= support, ioremap exec fix - 1 - --- 2020-02-15 Jan Kiszka New
[v2,1/3] riscv: Add support for mem= riscv: mem= support, ioremap exec fix - 1 - --- 2020-02-15 Jan Kiszka New
riscv: Add support for mem= riscv: Add support for mem= - - - --- 2020-02-14 Jan Kiszka New
[10/10] riscv: create a loader.bin for the kendryte kflash.py tool Kendryte k210 SoC boards support - 2 - --- 2020-02-12 Damien Le Moal New
[09/10] riscv: Kendryte K210 default config Kendryte k210 SoC boards support - 2 - --- 2020-02-12 Damien Le Moal New
[08/10] riscv: Add Kendryte K210 device tree Kendryte k210 SoC boards support - 1 - --- 2020-02-12 Damien Le Moal New
[07/10] riscv: Select required drivers for Kendryte SOC Kendryte k210 SoC boards support - 2 - --- 2020-02-12 Damien Le Moal New
[06/10] riscv: Add Kendryte K210 SoC support Kendryte k210 SoC boards support 1 1 - --- 2020-02-12 Damien Le Moal New
[05/10] riscv: Add SOC early init support Kendryte k210 SoC boards support - 1 - --- 2020-02-12 Damien Le Moal New
[04/10] riscv: Add BUILTIN_DTB support Kendryte k210 SoC boards support - 1 - --- 2020-02-12 Damien Le Moal New
[03/10] riscv: Unaligned load/store handling for M_MODE Kendryte k210 SoC boards support - 1 - --- 2020-02-12 Damien Le Moal New
[02/10] riscv: Force flat memory model with no-mmu Kendryte k210 SoC boards support - 2 - --- 2020-02-12 Damien Le Moal New
[01/10] riscv: Fix gitignore Kendryte k210 SoC boards support - - - --- 2020-02-12 Damien Le Moal New
[v8,11/11] RISC-V: Support cpu hotplug Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-12 Atish Patra New
[v8,10/11] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Add support for SBI v0.2 and CPU hotplug - - - --- 2020-02-12 Atish Patra New
[v8,09/11] RISC-V: Add supported for ordered booting method using HSM Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-12 Atish Patra New
[v8,08/11] RISC-V: Add SBI HSM extension Add support for SBI v0.2 and CPU hotplug - - - --- 2020-02-12 Atish Patra New
[v8,07/11] RISC-V: Add cpu_ops and modify default booting method Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-12 Atish Patra New
[v8,06/11] RISC-V: Move relocate and few other functions out of __init Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-12 Atish Patra New
[v8,05/11] RISC-V: Implement new SBI v0.2 extensions Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-12 Atish Patra New
[v8,04/11] RISC-V: Introduce a new config for SBI v0.1 Add support for SBI v0.2 and CPU hotplug - 1 - --- 2020-02-12 Atish Patra New
[v8,03/11] RISC-V: Add SBI v0.2 extension definitions Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-12 Atish Patra New
[v8,02/11] RISC-V: Add basic support for SBI v0.2 Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-12 Atish Patra New
[v8,01/11] RISC-V: Mark existing SBI as 0.1 SBI. Add support for SBI v0.2 and CPU hotplug - 2 - --- 2020-02-12 Atish Patra New
[v2,2/2] riscv: Use macro definition instead of magic number RISC-V page table dumper - - - --- 2020-02-10 Zong Li New
[v2,1/2] riscv: Add support to dump the kernel page tables RISC-V page table dumper - - 1 --- 2020-02-10 Zong Li New
[v2,2/2] riscv: adjust the indent Fix the page table size of KASAN use. - - - --- 2020-02-10 Zong Li New
[v2,1/2] riscv: allocate a complete page size for each page table Fix the page table size of KASAN use. - - - --- 2020-02-10 Zong Li New
riscv: fix seccomp reject syscall code path riscv: fix seccomp reject syscall code path - 1 - --- 2020-02-08 Tycho Andersen New
[2/2] riscv: adjust the indent Fix the page table size of KASAN use. - - - --- 2020-02-07 Zong Li New
[1/2] riscv: allocate a complete page size for each page table Fix the page table size of KASAN use. - - - --- 2020-02-07 Zong Li New
[V13] mm/debug: Add tests validating architecture page table helpers [V13] mm/debug: Add tests validating architecture page table helpers - 1 2 --- 2020-02-05 Anshuman Khandual New
riscv: force hart_lottery to put in .sdata section riscv: force hart_lottery to put in .sdata section - 2 - --- 2020-02-04 Zong Li New
RISC-V: Don't enable all interrupts in trap_init() RISC-V: Don't enable all interrupts in trap_init() - 2 1 --- 2020-02-02 Anup Patel New
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