Show patches with: Submitter = Jisheng Zhang       |    State = Action Required       |    Archived = No       |   18 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,2/2] serial: 8250_early: add xscale earlycon support serial: 8250: move mmp|pxa uart earlycon code and add xscale earlycon - - - 121- 2024-07-11 Jisheng Zhang New
[v2,1/2] serial: 8250: move mmp|pxa uart earlycon code serial: 8250: move mmp|pxa uart earlycon code and add xscale earlycon - - - 121- 2024-07-11 Jisheng Zhang New
[v2,2/2] riscv: select ARCH_USE_SYM_ANNOTATIONS riscv: select ARCH_USE_SYM_ANNOTATIONS - 1 - 121- 2024-07-09 Jisheng Zhang New
[v2,1/2] riscv: errata: sifive: Use SYM_*() assembly macros riscv: select ARCH_USE_SYM_ANNOTATIONS - 1 - 121- 2024-07-09 Jisheng Zhang New
[v2] riscv: define ILLEGAL_POINTER_VALUE for 64bit [v2] riscv: define ILLEGAL_POINTER_VALUE for 64bit - - - 13-- 2024-07-05 Jisheng Zhang New
[4/4] riscv: uaccess: use 'asm goto output' for get_user riscv: uaccess: optimizations - - - 1012 2024-06-25 Jisheng Zhang New
[3/4] riscv: uaccess: use 'asm goto' for put_user() riscv: uaccess: optimizations - - - 1012 2024-06-25 Jisheng Zhang New
[2/4] riscv: uaccess: use input constraints for ptr of __put_user riscv: uaccess: optimizations - - - 12-1 2024-06-25 Jisheng Zhang New
[1/4] riscv: implement user_access_begin and families riscv: uaccess: optimizations - 1 - 10-3 2024-06-25 Jisheng Zhang New
[v2] riscv: enable HAVE_ARCH_STACKLEAK [v2] riscv: enable HAVE_ARCH_STACKLEAK - 1 - 13-- 2024-06-23 Jisheng Zhang New
[6/6] riscv: remove asmlinkage from updated functions riscv: convert bottom half of exception handling to C - - - 13-- 2024-06-16 Jisheng Zhang New
[5/6] riscv: errata: sifive: remove NOMMU handling riscv: convert bottom half of exception handling to C - - - 13-- 2024-06-16 Jisheng Zhang New
[4/6] riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT riscv: convert bottom half of exception handling to C - - - 13-- 2024-06-16 Jisheng Zhang New
[3/6] riscv: convert bottom half of exception handling to C riscv: convert bottom half of exception handling to C - - - 121- 2024-06-16 Jisheng Zhang New
[2/6] riscv: avoid corrupting the RAS riscv: convert bottom half of exception handling to C - 1 - 13-- 2024-06-16 Jisheng Zhang New
[1/6] riscv: Improve exception and system call latency riscv: convert bottom half of exception handling to C - 1 - 13-- 2024-06-16 Jisheng Zhang New
irqchip/riscv-intc: Remove asmlinkage irqchip/riscv-intc: Remove asmlinkage - 1 - 13-- 2024-06-14 Jisheng Zhang New
[RESEND] riscv: boot: remove duplicated targets line [RESEND] riscv: boot: remove duplicated targets line - 1 - 13-- 2024-06-13 Jisheng Zhang New