Show patches with: Submitter = Jisheng Zhang       |    Archived = No       |   303 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
riscv: boot: remove duplicated targets line riscv: boot: remove duplicated targets line - 1 - 13-- 2024-04-14 Jisheng Zhang New
[v3,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint riscv: improve nommu and timer-clint - - - --1 2024-04-10 Jisheng Zhang New
[v3,1/2] riscv: nommu: remove PAGE_OFFSET hardcoding riscv: improve nommu and timer-clint - - - --1 2024-04-10 Jisheng Zhang New
[v3,RESEND,2/2] riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} riscv: enable lockless lockref implementation - 1 - --- 2024-03-25 Jisheng Zhang New
[v3,RESEND,1/2] riscv: select ARCH_USE_CMPXCHG_LOCKREF riscv: enable lockless lockref implementation - 1 - --- 2024-03-25 Jisheng Zhang New
[v3,RESEND] riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required [v3,RESEND] riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required - 1 - 13-- 2024-03-25 Jisheng Zhang New
[v3,RESEND] riscv: select ARCH_HAS_FAST_MULTIPLIER [v3,RESEND] riscv: select ARCH_HAS_FAST_MULTIPLIER - 2 1 13-- 2024-03-25 Jisheng Zhang New
[v2] riscv: Use asm-generic for {read,write}{bwlq} and their relaxed variant [v2] riscv: Use asm-generic for {read,write}{bwlq} and their relaxed variant - 1 - 13-- 2023-12-02 Jisheng Zhang New
[v2,RESEND] riscv: mm: implement pgprot_nx [v2,RESEND] riscv: mm: implement pgprot_nx - 3 1 --- 2024-03-25 Jisheng Zhang Accepted
[v4,2/2] riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW riscv: enable EFFICIENT_UNALIGNED_ACCESS and DCACHE_WORD_ACCESS - - - 11-2 2023-12-25 Jisheng Zhang Accepted
[v4,1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS riscv: enable EFFICIENT_UNALIGNED_ACCESS and DCACHE_WORD_ACCESS - 2 - 12-1 2023-12-25 Jisheng Zhang Accepted
[4/4] riscv: enable HAVE_FAST_GUP if MMU riscv: support fast gup - 1 - 13-- 2023-12-19 Jisheng Zhang Accepted
[3/4] riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU riscv: support fast gup - 1 - 13-- 2023-12-19 Jisheng Zhang Accepted
[2/4] riscv: tlb: convert __p*d_free_tlb() to inline functions riscv: support fast gup - 1 - 13-- 2023-12-19 Jisheng Zhang Accepted
[1/4] riscv: tlb: fix __p*d_free_tlb() riscv: support fast gup - 1 - 13-- 2023-12-19 Jisheng Zhang Accepted
riscv: Select ARCH_WANTS_NO_INSTR riscv: Select ARCH_WANTS_NO_INSTR - - - 13-- 2023-11-23 Jisheng Zhang Accepted
riscv: mm: implement pgprot_nx riscv: mm: implement pgprot_nx - 3 1 13-- 2023-11-21 Jisheng Zhang Accepted
[RESEND,v4,2/2] riscv: errata: thead: use pa based instructions for CMO riscv: errata: thead: use riscv_nonstd_cache_ops for CMO - 1 - 12-1 2023-11-14 Jisheng Zhang Accepted
[RESEND,v4,1/2] riscv: errata: thead: use riscv_nonstd_cache_ops for CMO riscv: errata: thead: use riscv_nonstd_cache_ops for CMO - 1 1 11-2 2023-11-14 Jisheng Zhang Accepted
[v2,5/5] riscv: dts: sophgo: add Milk-V Duo board device tree Add Milk-V Duo board support 1 - - --1 2023-10-06 Jisheng Zhang Accepted
[v2,4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree Add Milk-V Duo board support 1 - - --1 2023-10-06 Jisheng Zhang Accepted
[v2,3/5] dt-bindings: riscv: Add Milk-V Duo board compatibles Add Milk-V Duo board support 2 - - --1 2023-10-06 Jisheng Zhang Accepted
[v2,2/5] dt-bindings: timer: Add SOPHGO CV1800B clint Add Milk-V Duo board support 1 - - --1 2023-10-06 Jisheng Zhang Accepted
[v2,1/5] dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic Add Milk-V Duo board support 1 - - --1 2023-10-06 Jisheng Zhang Accepted
soc: renesas: make ARCH_R9A07G043 (riscv version) depend on NONPORTABLE soc: renesas: make ARCH_R9A07G043 (riscv version) depend on NONPORTABLE - 2 1 14-- 2023-10-04 Jisheng Zhang Accepted
riscv: don't probe unaligned access speed if already done riscv: don't probe unaligned access speed if already done - 1 - 24-6 2023-09-12 Jisheng Zhang Accepted
[v2] riscv: mm: update T-Head memory type definitions [v2] riscv: mm: update T-Head memory type definitions - 1 1 8-6 2023-09-12 Jisheng Zhang Accepted
[v3] riscv: errata: fix T-Head dcache.cva encoding [v3] riscv: errata: fix T-Head dcache.cva encoding - 2 2 --- 2023-09-12 Jisheng Zhang Accepted
[v2] riscv: dts: thead: set dma-noncoherent to soc bus [v2] riscv: dts: thead: set dma-noncoherent to soc bus - 1 1 14-- 2023-09-12 Jisheng Zhang conchuod Accepted
[RESEND,3/3] riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr riscv: vdso.lds.S: some improvement - 1 1 24-6 2023-09-12 Jisheng Zhang Accepted
[RESEND,2/3] riscv: vdso.lds.S: merge .data section into .rodata section riscv: vdso.lds.S: some improvement - - 1 24-6 2023-09-12 Jisheng Zhang Accepted
[RESEND,1/3] riscv: vdso.lds.S: drop __alt_start and __alt_end symbols riscv: vdso.lds.S: some improvement - - 1 24-6 2023-09-12 Jisheng Zhang Accepted
[v2,2/2] riscv: errata: prefix T-Head mnemonics with th. riscv: errata: improve T-Head CMO - 1 - 15-1 2023-08-27 Jisheng Zhang Accepted
[v2,1/2] riscv: errata: fix T-Head dcache.cva encoding riscv: errata: improve T-Head CMO - 2 2 16-- 2023-08-27 Jisheng Zhang Accepted
riscv: enable DEBUG_FORCE_FUNCTION_ALIGN_64B riscv: enable DEBUG_FORCE_FUNCTION_ALIGN_64B - 1 - 16-- 2023-07-27 Jisheng Zhang Accepted
[v3,2/2] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 16-- 2023-07-18 Jisheng Zhang Accepted
[v3,1/2] riscv: allow kmalloc() caches aligned to the smallest value riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 16-- 2023-07-18 Jisheng Zhang Accepted
[v2] riscv: support PREEMPT_DYNAMIC with static keys [v2] riscv: support PREEMPT_DYNAMIC with static keys - 1 - 16-- 2023-07-16 Jisheng Zhang Accepted
riscv: mm: fix truncates issue on RV32 riscv: mm: fix truncates issue on RV32 - - - 16-- 2023-07-09 Jisheng Zhang Accepted
[v3,8/8] riscv: defconfig: enable T-HEAD SoC Add Sipeed Lichee Pi 4A RISC-V board support 2 1 - --1 2023-06-17 Jisheng Zhang Accepted
[v3,7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Add Sipeed Lichee Pi 4A RISC-V board support 1 - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,4/8] riscv: Add the T-HEAD SoC family Kconfig option Add Sipeed Lichee Pi 4A RISC-V board support - 1 - --1 2023-06-17 Jisheng Zhang Accepted
[v3,3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Add Sipeed Lichee Pi 4A RISC-V board support - 1 - --1 2023-06-17 Jisheng Zhang Accepted
[v3,1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Add Sipeed Lichee Pi 4A RISC-V board support - 2 - --1 2023-06-17 Jisheng Zhang Accepted
[3/3] riscv: mm: mark noncoherent_supported as __ro_after_init riscv: some CMO alternative related clean up - 1 - 16-- 2023-06-14 Jisheng Zhang Accepted
[2/3] riscv: mm: mark CBO relate initialization funcs as __init riscv: some CMO alternative related clean up - 1 - 16-- 2023-06-14 Jisheng Zhang Accepted
[1/3] riscv: errata: thead: only set cbom size & noncoherent during boot riscv: some CMO alternative related clean up - 1 - 151- 2023-06-14 Jisheng Zhang Accepted
riscv: mm: try VMA lock-based page fault handling first riscv: mm: try VMA lock-based page fault handling first - 3 - 16-- 2023-05-23 Jisheng Zhang Accepted
[v2] riscv: mm: stub extable related functions/macros for !MMU [v2] riscv: mm: stub extable related functions/macros for !MMU - - - 17-- 2023-05-09 Jisheng Zhang palmer Accepted
[v5,13/13] riscv: remove riscv_isa_ext_keys[] array and related usage riscv: improve boot time isa extensions handling - 4 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() riscv: improve boot time isa extensions handling 1 1 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() riscv: improve boot time isa extensions handling - 4 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,10/13] riscv: alternative: patch alternatives in the vDSO riscv: improve boot time isa extensions handling - 2 - 161- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,09/13] riscv: switch to relative alternative entries riscv: improve boot time isa extensions handling - 2 - 161- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,08/13] riscv: module: Add ADD16 and SUB16 rela types riscv: improve boot time isa extensions handling - 1 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,07/13] riscv: module: move find_section to module.h riscv: improve boot time isa extensions handling - 2 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() riscv: improve boot time isa extensions handling - 3 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,05/13] riscv: introduce riscv_has_extension_[un]likely() riscv: improve boot time isa extensions handling 1 1 - 161- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,04/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions riscv: improve boot time isa extensions handling - 2 - 161- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,03/13] riscv: hwcap: make ISA extension ids can be used in asm riscv: improve boot time isa extensions handling - 3 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,02/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier riscv: improve boot time isa extensions handling - 3 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,01/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe riscv: improve boot time isa extensions handling - 2 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v2,5/5] riscv: select ARCH_WANT_LD_ORPHAN_WARN for !XIP_KERNEL riscv: improve link and support ARCH_WANT_LD_ORPHAN_WARN - 1 - 17-- 2023-01-19 Jisheng Zhang palmer Accepted
[v2,4/5] riscv: vmlinux.lds.S: explicitly catch .init.bss sections from EFI stub riscv: improve link and support ARCH_WANT_LD_ORPHAN_WARN - - - 17-- 2023-01-19 Jisheng Zhang palmer Accepted
[v2,3/5] riscv: vmlinux.lds.S: explicitly catch .riscv.attributes sections riscv: improve link and support ARCH_WANT_LD_ORPHAN_WARN - - - 17-- 2023-01-19 Jisheng Zhang palmer Accepted
[v2,2/5] riscv: vmlinux.lds.S: explicitly catch .rela.dyn symbols riscv: improve link and support ARCH_WANT_LD_ORPHAN_WARN - - - 17-- 2023-01-19 Jisheng Zhang palmer Accepted
[v2,1/5] riscv: lds: define RUNTIME_DISCARD_EXIT riscv: improve link and support ARCH_WANT_LD_ORPHAN_WARN - 1 - 17-- 2023-01-19 Jisheng Zhang palmer Accepted
riscv: alternative: proceed one more instruction for auipc/jalr pair riscv: alternative: proceed one more instruction for auipc/jalr pair - 2 - --1 2023-01-15 Jisheng Zhang palmer Accepted
riscv: boot: add zstd support riscv: boot: add zstd support - - - 16-- 2022-11-23 Jisheng Zhang palmer Accepted
[v2] riscv: vdso: fix section overlapping under some conditions [v2] riscv: vdso: fix section overlapping under some conditions - - - 1211 2022-11-02 Jisheng Zhang palmer Accepted
riscv: vdso: fix build with llvm riscv: vdso: fix build with llvm - - 1 12-2 2022-10-31 Jisheng Zhang palmer Accepted
riscv: process: fix kernel info leakage riscv: process: fix kernel info leakage - - 1 1111 2022-10-29 Jisheng Zhang palmer Accepted
riscv: remove special treatment for the link order of head.o riscv: remove special treatment for the link order of head.o - - - --- 2022-10-18 Jisheng Zhang palmer Accepted
[v2] riscv: jump_label: mark arguments as const to satisfy asm constraints [v2] riscv: jump_label: mark arguments as const to satisfy asm constraints - 1 1 --- 2022-10-08 Jisheng Zhang Accepted
[v3] riscv: enable THP_SWAP for RV64 [v3] riscv: enable THP_SWAP for RV64 - 2 - --- 2022-08-29 Jisheng Zhang Accepted
riscv: compat: s/failed/unsupported if compat mode isn't supported riscv: compat: s/failed/unsupported if compat mode isn't supported 1 - - --- 2022-08-21 Jisheng Zhang Accepted
riscv: head: use 0 as the default text_offset riscv: head: use 0 as the default text_offset - - - 16-- 2022-11-28 Jisheng Zhang Rejected
[v3,6/6] riscv: dts: starfive: add Milkv Mars board device tree riscv: dts: starfive: add Milkv Mars board device tree - - - 1012 2024-01-31 Jisheng Zhang conchuod Changes Requested
[v3,5/6] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards riscv: dts: starfive: add Milkv Mars board device tree - - - 1111 2024-01-31 Jisheng Zhang conchuod Changes Requested
[v3,4/6] riscv: dts: starfive: visionfive 2: use cpus label for timebase freq riscv: dts: starfive: add Milkv Mars board device tree - 1 - 12-1 2024-01-31 Jisheng Zhang conchuod Changes Requested
[v3,3/6] riscv: dts: starfive: visionfive 2: update sound and codec dt node name riscv: dts: starfive: add Milkv Mars board device tree - 1 - 12-1 2024-01-31 Jisheng Zhang conchuod Changes Requested
[v3,2/6] dt-bindings: riscv: starfive: add Milkv Mars board riscv: dts: starfive: add Milkv Mars board device tree 1 1 - 12-1 2024-01-31 Jisheng Zhang conchuod Changes Requested
[v3,1/6] riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi riscv: dts: starfive: add Milkv Mars board device tree - 1 - 12-1 2024-01-31 Jisheng Zhang conchuod Changes Requested
[3/3] riscv: optimized memset riscv: optimize memcpy/memmove/memset - - - 913 2024-01-28 Jisheng Zhang Changes Requested
[2/3] riscv: optimized memmove riscv: optimize memcpy/memmove/memset - - - 914 2024-01-28 Jisheng Zhang Changes Requested
[1/3] riscv: optimized memcpy riscv: optimize memcpy/memmove/memset - - - 913 2024-01-28 Jisheng Zhang Changes Requested
[2/2] nvmem: Add Sophgo eFuse driver nvmem: Add Sophgo eFuse driver - - - 112- 2023-11-19 Jisheng Zhang Changes Requested
[1/2] dt-bindings: nvmem: Add sophgo,efuses nvmem: Add Sophgo eFuse driver - - - 112- 2023-11-19 Jisheng Zhang Changes Requested
[2/2] riscv: dts: sophgo: set pinctrl for uart0 riscv: sophgo: add pinctrl support for cv1800b - - - --1 2023-11-13 Jisheng Zhang conchuod Changes Requested
[1/2] riscv: dts: cv1800b: add pinctrl node for cv1800b riscv: sophgo: add pinctrl support for cv1800b - - - --1 2023-11-13 Jisheng Zhang conchuod Changes Requested
[4/4] riscv: dts: sophgo: add reset phandle to all uart nodes riscv: sophgo: add reset support for cv1800b - - - 8-5 2023-11-13 Jisheng Zhang Changes Requested
[3/4] riscv: dts: sophgo: add reset dt node for cv1800b riscv: sophgo: add reset support for cv1800b - - - 12-1 2023-11-13 Jisheng Zhang Changes Requested
[2/4] reset: Add reset controller support for Sophgo CV1800B SoC riscv: sophgo: add reset support for cv1800b - - - 12-1 2023-11-13 Jisheng Zhang Changes Requested
[1/4] dt-bindings: reset: Add binding for Sophgo CV1800B reset controller riscv: sophgo: add reset support for cv1800b - 1 - 1111 2023-11-13 Jisheng Zhang Changes Requested
[v2,4/4] riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 2 1 --1 2023-05-23 Jisheng Zhang Changes Requested
[v2,3/4] vmlinux.lds.h: use correct .init.data.* section name riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 1 - --1 2023-05-23 Jisheng Zhang Changes Requested
[v2,2/4] riscv: vmlinux-xip.lds.S: remove .alternative section riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 2 - --1 2023-05-23 Jisheng Zhang Changes Requested
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