Show patches with: Submitter = Jisheng Zhang       |    Archived = No       |   303 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[1/5] dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic Add Milk-V Duo board support 1 - - --1 2023-09-30 Jisheng Zhang conchuod Superseded
[2/2] pwm: add T-HEAD PWM driver pwm: add driver for T-THEAD TH1520 SoC - - - --- 2023-09-28 Jisheng Zhang Superseded
[1/2] dt-bindings: pwm: Add T-HEAD PWM controller pwm: add driver for T-THEAD TH1520 SoC - - - --- 2023-09-28 Jisheng Zhang Superseded
[2/2] usb: dwc3: add T-HEAD TH1520 usb driver usb: dwc3: add driver for T-HEAD TH1520 SoC - - - 151- 2023-09-27 Jisheng Zhang Handled Elsewhere
[1/2] dt-bindings: usb: Add T-HEAD TH1520 USB controller usb: dwc3: add driver for T-HEAD TH1520 SoC - - - 151- 2023-09-27 Jisheng Zhang Handled Elsewhere
riscv: don't probe unaligned access speed if already done riscv: don't probe unaligned access speed if already done - 1 - 24-6 2023-09-12 Jisheng Zhang Accepted
riscv: errata: thead: use riscv_nonstd_cache_ops for CMO riscv: errata: thead: use riscv_nonstd_cache_ops for CMO - - 1 --1 2023-09-12 Jisheng Zhang Superseded
[v2] riscv: mm: update T-Head memory type definitions [v2] riscv: mm: update T-Head memory type definitions - 1 1 8-6 2023-09-12 Jisheng Zhang Accepted
[v3] riscv: errata: fix T-Head dcache.cva encoding [v3] riscv: errata: fix T-Head dcache.cva encoding - 2 2 --- 2023-09-12 Jisheng Zhang Accepted
[v2] riscv: dts: thead: set dma-noncoherent to soc bus [v2] riscv: dts: thead: set dma-noncoherent to soc bus - 1 1 14-- 2023-09-12 Jisheng Zhang conchuod Accepted
[RESEND,3/3] riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr riscv: vdso.lds.S: some improvement - 1 1 24-6 2023-09-12 Jisheng Zhang Accepted
[RESEND,2/3] riscv: vdso.lds.S: merge .data section into .rodata section riscv: vdso.lds.S: some improvement - - 1 24-6 2023-09-12 Jisheng Zhang Accepted
[RESEND,1/3] riscv: vdso.lds.S: drop __alt_start and __alt_end symbols riscv: vdso.lds.S: some improvement - - 1 24-6 2023-09-12 Jisheng Zhang Accepted
[v2,2/2] riscv: errata: prefix T-Head mnemonics with th. riscv: errata: improve T-Head CMO - 1 - 15-1 2023-08-27 Jisheng Zhang Accepted
[v2,1/2] riscv: errata: fix T-Head dcache.cva encoding riscv: errata: improve T-Head CMO - 2 2 16-- 2023-08-27 Jisheng Zhang Accepted
riscv: mm: update T-Head memory type definitions riscv: mm: update T-Head memory type definitions - 1 1 16-- 2023-08-27 Jisheng Zhang Superseded
[net-next,3/3] net: stmmac: add glue layer for T-HEAD TH1520 SoC add the dwmac driver for T-HEAD TH1520 SoC - - - 1312 2023-08-20 Jisheng Zhang Handled Elsewhere
[net-next,2/3] dt-bindings: net: add T-HEAD dwmac support add the dwmac driver for T-HEAD TH1520 SoC - - - 151- 2023-08-20 Jisheng Zhang Handled Elsewhere
[net-next,1/3] dt-bindings: net: snps,dwmac: allow dwmac-3.70a to set pbl properties add the dwmac driver for T-HEAD TH1520 SoC - 1 - 16-- 2023-08-20 Jisheng Zhang Handled Elsewhere
riscv: enable DEBUG_FORCE_FUNCTION_ALIGN_64B riscv: enable DEBUG_FORCE_FUNCTION_ALIGN_64B - 1 - 16-- 2023-07-27 Jisheng Zhang Accepted
[3/3] riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr riscv: vdso.lds.S: some improvement - 1 - 16-- 2023-07-26 Jisheng Zhang Superseded
[2/3] riscv: vdso.lds.S: merge .data section into .rodata section riscv: vdso.lds.S: some improvement - - - 16-- 2023-07-26 Jisheng Zhang Superseded
[1/3] riscv: vdso.lds.S: drop __alt_start and __alt_end symbols riscv: vdso.lds.S: some improvement - - - 16-- 2023-07-26 Jisheng Zhang Superseded
[v3,2/2] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 16-- 2023-07-18 Jisheng Zhang Accepted
[v3,1/2] riscv: allow kmalloc() caches aligned to the smallest value riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 16-- 2023-07-18 Jisheng Zhang Accepted
[v2,2/2] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 16-- 2023-07-16 Jisheng Zhang Superseded
[v2,1/2] riscv: allow kmalloc() caches aligned to the smallest value riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - - - 15-1 2023-07-16 Jisheng Zhang Superseded
[v2] riscv: support PREEMPT_DYNAMIC with static keys [v2] riscv: support PREEMPT_DYNAMIC with static keys - 1 - 16-- 2023-07-16 Jisheng Zhang Accepted
riscv: mm: fix truncates issue on RV32 riscv: mm: fix truncates issue on RV32 - - - 16-- 2023-07-09 Jisheng Zhang Accepted
riscv: support PREEMPT_DYNAMIC with static keys riscv: support PREEMPT_DYNAMIC with static keys - - - 16-- 2023-07-09 Jisheng Zhang Superseded
[v3,8/8] riscv: defconfig: enable T-HEAD SoC Add Sipeed Lichee Pi 4A RISC-V board support 2 1 - --1 2023-06-17 Jisheng Zhang Accepted
[v3,7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Add Sipeed Lichee Pi 4A RISC-V board support 1 - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,4/8] riscv: Add the T-HEAD SoC family Kconfig option Add Sipeed Lichee Pi 4A RISC-V board support - 1 - --1 2023-06-17 Jisheng Zhang Accepted
[v3,3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-06-17 Jisheng Zhang Accepted
[v3,2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Add Sipeed Lichee Pi 4A RISC-V board support - 1 - --1 2023-06-17 Jisheng Zhang Accepted
[v3,1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Add Sipeed Lichee Pi 4A RISC-V board support - 2 - --1 2023-06-17 Jisheng Zhang Accepted
[3/3] riscv: mm: mark noncoherent_supported as __ro_after_init riscv: some CMO alternative related clean up - 1 - 16-- 2023-06-14 Jisheng Zhang Accepted
[2/3] riscv: mm: mark CBO relate initialization funcs as __init riscv: some CMO alternative related clean up - 1 - 16-- 2023-06-14 Jisheng Zhang Accepted
[1/3] riscv: errata: thead: only set cbom size & noncoherent during boot riscv: some CMO alternative related clean up - 1 - 151- 2023-06-14 Jisheng Zhang Accepted
[6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - - - 13-3 2023-05-26 Jisheng Zhang Superseded
[5/6] riscv: allow kmalloc() caches aligned to the smallest value riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - - - 13-3 2023-05-26 Jisheng Zhang Superseded
[4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - - - 16-- 2023-05-26 Jisheng Zhang Superseded
[3/6] riscv: mm: mark noncoherent_supported as __ro_after_init riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 16-- 2023-05-26 Jisheng Zhang Superseded
[2/6] riscv: mm: mark CBO relate initialization funcs as __init riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 16-- 2023-05-26 Jisheng Zhang Superseded
[1/6] riscv: errata: thead: only set cbom size & noncoherent during boot riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 - 1 - 151- 2023-05-26 Jisheng Zhang Superseded
riscv: mm: try VMA lock-based page fault handling first riscv: mm: try VMA lock-based page fault handling first - 3 - 16-- 2023-05-23 Jisheng Zhang Accepted
[v2,4/4] riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 2 1 --1 2023-05-23 Jisheng Zhang Changes Requested
[v2,3/4] vmlinux.lds.h: use correct .init.data.* section name riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 1 - --1 2023-05-23 Jisheng Zhang Changes Requested
[v2,2/4] riscv: vmlinux-xip.lds.S: remove .alternative section riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 2 - --1 2023-05-23 Jisheng Zhang Changes Requested
[v2,1/4] riscv: move options to keep entries sorted riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION 1 1 - --1 2023-05-23 Jisheng Zhang Changes Requested
[v2,9/9] riscv: defconfig: enable T-HEAD SoC Add Sipeed Lichee Pi 4A RISC-V board support 2 1 - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC Add Sipeed Lichee Pi 4A RISC-V board support 1 - - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,7/9] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,5/9] riscv: Add the T-HEAD SoC family Kconfig option Add Sipeed Lichee Pi 4A RISC-V board support - 1 - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,4/9] dt-binding: riscv: add T-HEAD CPU reset Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Add Sipeed Lichee Pi 4A RISC-V board support - - - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,2/9] dt-bindings: timer: Add T-HEAD TH1520 clint Add Sipeed Lichee Pi 4A RISC-V board support - 1 - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v2,1/9] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Add Sipeed Lichee Pi 4A RISC-V board support - 2 - --1 2023-05-18 Jisheng Zhang conchuod Superseded
[v4,10/10] riscv: defconfig: enable BOUFFALOLAB SoC riscv: add Bouffalolab bl808 support 1 1 - 16-- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,09/10] MAINTAINERS: riscv: add entry for Bouffalolab SoC riscv: add Bouffalolab bl808 support 1 1 - 16-- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,08/10] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree riscv: add Bouffalolab bl808 support 1 - - 151- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,07/10] riscv: dts: bouffalolab: add the bl808 SoC base device tree riscv: add Bouffalolab bl808 support 1 - - 151- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,06/10] dt-bindings: riscv: Add bouffalolab bl808 board compatibles riscv: add Bouffalolab bl808 support 1 1 - 151- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,05/10] riscv: add the Bouffalolab SoC family Kconfig option riscv: add Bouffalolab bl808 support 1 1 - 151- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,04/10] serial: bflb_uart: add Bouffalolab UART Driver riscv: add Bouffalolab bl808 support - - - 151- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,03/10] dt-bindings: serial: add documentation for Bouffalolab UART Driver riscv: add Bouffalolab bl808 support 1 1 - 151- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,02/10] dt-bindings: interrupt-controller: Add bouffalolab bl808 plic riscv: add Bouffalolab bl808 support - 2 - 16-- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v4,01/10] dt-bindings: vendor-prefixes: add bouffalolab riscv: add Bouffalolab bl808 support 2 1 - 16-- 2023-05-18 Jisheng Zhang conchuod Changes Requested
[v3,10/10] riscv: defconfig: enable BOUFFALOLAB SoC riscv: add Bouffalolab bl808 support 1 1 - 14-2 2023-05-14 Jisheng Zhang conchuod Superseded
[v3,09/10] MAINTAINERS: riscv: add entry for Bouffalolab SoC riscv: add Bouffalolab bl808 support 1 1 - 14-2 2023-05-14 Jisheng Zhang conchuod Superseded
[v3,08/10] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree riscv: add Bouffalolab bl808 support 1 - - 1312 2023-05-14 Jisheng Zhang conchuod Superseded
[v3,07/10] riscv: dts: bouffalolab: add the bl808 SoC base device tree riscv: add Bouffalolab bl808 support 1 - - 1312 2023-05-14 Jisheng Zhang conchuod Superseded
[v3,06/10] dt-bindings: riscv: Add bouffalolab bl808 board compatibles riscv: add Bouffalolab bl808 support 1 1 - 1312 2023-05-14 Jisheng Zhang conchuod Superseded
[v3,05/10] riscv: add the Bouffalolab SoC family Kconfig option riscv: add Bouffalolab bl808 support 1 1 - 1312 2023-05-14 Jisheng Zhang conchuod Superseded
[v3,04/10] serial: bflb_uart: add Bouffalolab UART Driver riscv: add Bouffalolab bl808 support - - - 1312 2023-05-14 Jisheng Zhang Superseded
[v3,03/10] dt-bindings: serial: add documentation for Bouffalolab UART Driver riscv: add Bouffalolab bl808 support 1 - - 1411 2023-05-14 Jisheng Zhang Superseded
[v3,02/10] dt-bindings: interrupt-controller: Add bouffalolab bl808 plic riscv: add Bouffalolab bl808 support - 1 - 16-- 2023-05-14 Jisheng Zhang conchuod Superseded
[v3,01/10] dt-bindings: vendor-prefixes: add bouffalolab riscv: add Bouffalolab bl808 support 1 1 - 16-- 2023-05-14 Jisheng Zhang conchuod Superseded
[4/4] riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - - - --1 2023-05-11 Jisheng Zhang Superseded
[3/4] vmlinux.lds.h: use correct .init.data.* section name riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - - - --1 2023-05-11 Jisheng Zhang Superseded
[2/4] riscv: move HAVE_RETHOOK to keep entries sorted riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 1 - --1 2023-05-11 Jisheng Zhang Superseded
[1/4] riscv: vmlinux-xip.lds.S: remove .alternative section riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION - 1 - --1 2023-05-11 Jisheng Zhang Superseded
[RT,3/3] riscv: Allow to enable RT riscv: add PREEMPT_RT support - - - 16-- 2023-05-10 Jisheng Zhang Handled Elsewhere
[RT,2/3] riscv: add lazy preempt support riscv: add PREEMPT_RT support - - - 151- 2023-05-10 Jisheng Zhang Handled Elsewhere
[RT,1/3] asm-generic/preempt: also check preempt_lazy_count for should_resched() etc. riscv: add PREEMPT_RT support - - - 16-- 2023-05-10 Jisheng Zhang Handled Elsewhere
[v2] riscv: mm: stub extable related functions/macros for !MMU [v2] riscv: mm: stub extable related functions/macros for !MMU - - - 17-- 2023-05-09 Jisheng Zhang palmer Accepted
riscv: mm: stub extable related functions/macros for !MMU riscv: mm: stub extable related functions/macros for !MMU - - - 14-3 2023-05-09 Jisheng Zhang Superseded
[5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Add Sipeed Lichee Pi 4A RISC-V board support - - - --- 2023-05-07 Jisheng Zhang conchuod Superseded
[4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --- 2023-05-07 Jisheng Zhang conchuod Superseded
[3/5] riscv: dts: add initial T-HEAD light SoC device tree Add Sipeed Lichee Pi 4A RISC-V board support - - - --- 2023-05-07 Jisheng Zhang conchuod Superseded
[2/5] riscv: Add the T-HEAD SoC family Kconfig option Add Sipeed Lichee Pi 4A RISC-V board support - - - --- 2023-05-07 Jisheng Zhang conchuod Superseded
[1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Add Sipeed Lichee Pi 4A RISC-V board support - - - --- 2023-05-07 Jisheng Zhang conchuod Superseded
riscv: enable BUILDTIME_TABLE_SORT for !MMU riscv: enable BUILDTIME_TABLE_SORT for !MMU - - - 16-1 2023-04-09 Jisheng Zhang Changes Requested
[v5,13/13] riscv: remove riscv_isa_ext_keys[] array and related usage riscv: improve boot time isa extensions handling - 4 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() riscv: improve boot time isa extensions handling 1 1 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() riscv: improve boot time isa extensions handling - 4 - 17-- 2023-01-28 Jisheng Zhang palmer Accepted
[v5,10/13] riscv: alternative: patch alternatives in the vDSO riscv: improve boot time isa extensions handling - 2 - 161- 2023-01-28 Jisheng Zhang palmer Accepted
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