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Mon, 15 Apr 2019 04:41:35 -0700 (PDT) From: Yash Shah To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Subject: [PATCH 1/3] RISC-V: Add DT documentation for SiFive L2 Cache Controller Date: Mon, 15 Apr 2019 17:10:41 +0530 Message-Id: <1555328443-30874-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555328443-30874-1-git-send-email-yash.shah@sifive.com> References: <1555328443-30874-1-git-send-email-yash.shah@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_044136_400537_A1F14FAE X-CRM114-Status: GOOD ( 12.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, aou@eecs.berkeley.edu, palmer@sifive.com, sachin.ghadi@sifive.com, Yash Shah , robh+dt@kernel.org, bp@alien8.de, paul.walmsley@sifive.com, james.morse@arm.com, mchehab@kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds device tree bindings for SiFive FU540 L2 cache controller driver Signed-off-by: Yash Shah --- .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt new file mode 100644 index 0000000..15132e2 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt @@ -0,0 +1,53 @@ +SiFive L2 Cache Controller +-------------------------- +The SiFive Level 2 Cache Controller is used to provide access to fast copies +of memory for masters in a Core Complex. The Level 2 Cache Controller also +acts as directory-based coherency manager. + +Required Properties: +-------------------- +- compatible: Should be "sifive,fu540-c000-ccache" + +- cache-block-size: Specifies the block size in bytes of the cache + +- cache-level: Should be set to 2 for a level 2 cache + +- cache-sets: Specifies the number of associativity sets of the cache + +- cache-size: Specifies the size in bytes of the cache + +- cache-unified: Specifies the cache is a unified cache + +- interrupt-parent: Must be core interrupt controller + +- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) + +- reg: Physical base address and size of L2 cache controller registers map + +- reg-names: Should be "control" + +Optional Properties: +-------------------- +- next-level-cache: phandle to the next level cache if present. + +- memory-region: reference to the reserved-memory for the L2 Loosely Integrated + Memory region. The reserved memory node should be defined as per the bindings + in reserved-memory.txt + + +Example: + + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache"; + cache-block-size = <0x40>; + cache-level = <0x2>; + cache-sets = <0x400>; + cache-size = <0x100000>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + reg-names = "control"; + next-level-cache = <&L25 &L40 &L36>; + memory-region = <&l2_lim>; + };