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bh=T8hpdmPuZ0S4pAwGaFbzxGbWzGiaXVlLtVKlfYx4iio=; b=Diwlf163a28YOq4pVJ2mt1a45aSXgRDEMLXPb+dmRPCCxDu/iY/qFQA/vBwhlZdREQ lIwr4hIvIm0UHjIerCTLmbn1ayTUO03Hei9SkTBYrmc4F9R4BHYEvlhw7LHOd2B+v/Wr GBA+zbYYngMiGPkAd+xPxJAcTVXNyKQmCYnIp5/TR/JqqdOOFq/AKEEsTIe7AjSw+mpG 5VQDr5lt5Cngyn2S72+iKrslaGa9943Rw5gqik+Im7zTVtBYEch8gRJjpdjNKjzJAFPK Fp0zbiadmdGTPemVcRMjoA7uPlznsH4kQrJBOB0YSwDici8n08XGbmiFWhbqx3d3sYoE 5OtA== X-Gm-Message-State: APjAAAUjSRUedq2EFM7Lm71kHXjCa6x1gt0zpAdZpbKYKhiP7w0jb+f+ eOQ7yfZ05xu/LzbWe2aZZqCoOA== X-Google-Smtp-Source: APXvYqwvAjJnxUVsUW1uW8HJ+SfIt8h2TIyySZXIVTncALvvJkEVjE2ZgjSeTQHCUfvKmF5+rETmxg== X-Received: by 2002:a17:902:8609:: with SMTP id f9mr30112857plo.32.1557142062000; Mon, 06 May 2019 04:27:42 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id k4sm23990693pgh.27.2019.05.06.04.27.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 May 2019 04:27:40 -0700 (PDT) From: Yash Shah To: linux-edac@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@sifive.com, bp@alien8.de, james.morse@arm.com Subject: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs Date: Mon, 6 May 2019 16:57:06 +0530 Message-Id: <1557142026-15949-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1557142026-15949-1-git-send-email-yash.shah@sifive.com> References: <1557142026-15949-1-git-send-email-yash.shah@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190506_042742_903907_354B4716 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aou@eecs.berkeley.edu, paulmck@linux.ibm.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, nicolas.ferre@microchip.com, sachin.ghadi@sifive.com, Yash Shah , paul.walmsley@sifive.com, mchehab@kernel.org, davem@davemloft.net MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The initial ver of EDAC driver supports: - ECC event monitoring and reporting through the EDAC framework for SiFive L2 cache controller. The EDAC driver registers for notifier events from the L2 cache controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events Signed-off-by: Yash Shah Reviewed-by: James Morse Reviewed-by: James Morse --- This patch depends on patch 'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs' https://lkml.org/lkml/2019/5/6/255 MAINTAINERS | 6 +++ arch/riscv/Kconfig | 1 + drivers/edac/Kconfig | 6 +++ drivers/edac/Makefile | 1 + drivers/edac/sifive_edac.c | 119 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 133 insertions(+) create mode 100644 drivers/edac/sifive_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index ba4f104..50f9f43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5679,6 +5679,12 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/edac/sb_edac.c +EDAC-SIFIVE +M: Yash Shah +L: linux-edac@vger.kernel.org +S: Supported +F: drivers/edac/sifive_edac.c + EDAC-SKYLAKE M: Tony Luck L: linux-edac@vger.kernel.org diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index eb56c82..31999a6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -49,6 +49,7 @@ config RISCV select GENERIC_IRQ_MULTI_HANDLER select ARCH_HAS_PTE_SPECIAL select HAVE_EBPF_JIT if 64BIT + select EDAC_SUPPORT config MMU def_bool y diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 47eb4d1..3e05228 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,6 +460,12 @@ config EDAC_ALTERA_SDMMC Support for error detection and correction on the Altera SDMMC FIFO Memory for Altera SoCs. +config EDAC_SIFIVE + bool "Sifive platform EDAC driver" + depends on EDAC=y && RISCV + help + Support for error detection and correction on the SiFive SoCs. + config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" depends on ARCH_ZYNQ || ARCH_ZYNQMP diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 89ad4a84..165ca65e 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o obj-$(CONFIG_EDAC_THUNDERX) += thunderx_edac.o obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o +obj-$(CONFIG_EDAC_SIFIVE) += sifive_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c new file mode 100644 index 0000000..413cdb4 --- /dev/null +++ b/drivers/edac/sifive_edac.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SiFive Platform EDAC Driver + * + * Copyright (C) 2018-2019 SiFive, Inc. + * + * This driver is partially based on octeon_edac-pc.c + * + */ +#include +#include +#include "edac_module.h" +#include + +#define DRVNAME "sifive_edac" + +struct sifive_edac_priv { + struct notifier_block notifier; + struct edac_device_ctl_info *dci; +}; + +/** + * EDAC error callback + * + * @event: non-zero if unrecoverable. + */ +static +int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + const char *msg = (char *)ptr; + struct sifive_edac_priv *p; + + p = container_of(this, struct sifive_edac_priv, notifier); + + if (event == SIFIVE_L2_ERR_TYPE_UE) + edac_device_handle_ue(p->dci, 0, 0, msg); + else if (event == SIFIVE_L2_ERR_TYPE_CE) + edac_device_handle_ce(p->dci, 0, 0, msg); + + return NOTIFY_OK; +} + +static int ecc_register(struct platform_device *pdev) +{ + struct sifive_edac_priv *p; + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + p->notifier.notifier_call = ecc_err_event; + platform_set_drvdata(pdev, p); + + p->dci = edac_device_alloc_ctl_info(0, "sifive_ecc", 1, "sifive_ecc", + 1, 1, NULL, 0, + edac_device_alloc_index()); + if (IS_ERR(p->dci)) + return PTR_ERR(p->dci); + + p->dci->dev = &pdev->dev; + p->dci->mod_name = "Sifive ECC Manager"; + p->dci->ctl_name = dev_name(&pdev->dev); + p->dci->dev_name = dev_name(&pdev->dev); + + if (edac_device_add_device(p->dci)) { + dev_err(p->dci->dev, "failed to register with EDAC core\n"); + goto err; + } + + register_sifive_l2_error_notifier(&p->notifier); + + return 0; + +err: + edac_device_free_ctl_info(p->dci); + + return -ENXIO; +} + +static int ecc_unregister(struct platform_device *pdev) +{ + struct sifive_edac_priv *p = platform_get_drvdata(pdev); + + unregister_sifive_l2_error_notifier(&p->notifier); + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(p->dci); + + return 0; +} + +static struct platform_device *sifive_pdev; + +static int __init sifive_edac_init(void) +{ + int ret; + + sifive_pdev = platform_device_register_simple(DRVNAME, 0, NULL, 0); + if (IS_ERR(sifive_pdev)) + return PTR_ERR(sifive_pdev); + + ret = ecc_register(sifive_pdev); + if (ret) + platform_device_unregister(sifive_pdev); + + return ret; +} + +static void __exit sifive_edac_exit(void) +{ + ecc_unregister(sifive_pdev); + platform_device_unregister(sifive_pdev); +} + +module_init(sifive_edac_init); +module_exit(sifive_edac_exit); + +MODULE_AUTHOR("SiFive Inc."); +MODULE_DESCRIPTION("SiFive platform EDAC driver"); +MODULE_LICENSE("GPL v2");