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bh=Y+CmxvfTHNmkdcHZerrxb2wPdBc38Gq6FdKZioHxbqE=; b=Gm6pdY0ty0+NekAup0Ky4Ad3WjuVO4OSLjuDKGiSVs03SlTwwjEfWkexHj+/qlSPLF jvULmLLkNSmjfZ7JU9q8HuGiSI39taQrQQoFIFOUVmHRAOptFGULK2oP2trDO4FggiyB Ho/OLKzkIsz6OFoMFVlKFFBgySjT+HqeFLaePH3iojSPKJKcujjwWzSPeCn8DaDjK4kE sholjNq03c72RrrmXqxyIWKS5kRb7W5k/4vUHVZHR99PPS0mOezgP9ARdiWET1vHr5bE 9Z5adPiS8oVLCRshXoI063c5nzKRL6Qt9Dcx3OvEJc93GICVdx5z43QODOywY5aqVXHe lYuQ== X-Gm-Message-State: APjAAAVrYZ6Um2Xd4Y+EGFLPCiXqfa29XRP9U+5tOLzAC5rCBvgy1NVD nxnrEuaP4eZ2N87XJ1hXLer/aA== X-Google-Smtp-Source: APXvYqwGMFL+2bJhWMoeLMIUPikC9EIj+4FMNu3+vEguV2Ru2oTeOyZJqNVCOTuD3VLHeGb+B2sKMg== X-Received: by 2002:a63:dc50:: with SMTP id f16mr32511540pgj.447.1562092811827; Tue, 02 Jul 2019 11:40:11 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id e10sm15065327pfi.173.2019.07.02.11.40.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 Jul 2019 11:40:11 -0700 (PDT) From: Sagar Shrikant Kadam To: marek.vasut@gmail.com, tudor.ambarus@microchip.com, dwmw2@infradead.org, computersforpeace@gmail.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com Subject: [PATCH v7 1/4] mtd: spi-nor: add support for is25wp256 Date: Wed, 3 Jul 2019 00:09:02 +0530 Message-Id: <1562092745-11541-2-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1562092745-11541-1-git-send-email-sagar.kadam@sifive.com> References: <1562092745-11541-1-git-send-email-sagar.kadam@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190702_114016_226684_F55B64B6 X-CRM114-Status: GOOD ( 12.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aou@eecs.berkeley.edu, palmer@sifive.com, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Sagar Shrikant Kadam , paul.walmsley@sifive.com, linux-riscv@lists.infradead.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Update spi_nor_id table for is25wp256 (32MB) device from ISSI, present on HiFive Unleashed dev board (Rev: A00). Set method to enable quad mode for ISSI device in flash parameters table. Based on code originally written by Wesley Terpstra and/or Palmer Dabbelt https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Vignesh Raghavendra --- drivers/mtd/spi-nor/spi-nor.c | 9 ++++++++- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index e3a28c0..971f0f3 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1857,7 +1857,10 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - + { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES) + }, /* Macronix */ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, @@ -3687,6 +3690,10 @@ static int spi_nor_init_params(struct spi_nor *nor, case SNOR_MFR_ST: case SNOR_MFR_MICRON: break; + case SNOR_MFR_ISSI: + params->quad_enable = macronix_quad_enable; + break; + default: /* Kept only for backward compatibility purpose. */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b3d360b..b0e42b3 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -21,6 +21,7 @@ #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ +#define SNOR_MFR_ISSI 0x9d /* ISSI */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST