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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVu9N-0002YY-EF; Fri, 23 Oct 2020 10:18:21 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVu9K-0002XU-R9 for linux-riscv@lists.infradead.org; Fri, 23 Oct 2020 10:18:19 +0000 Received: from localhost.localdomain (unknown [42.120.72.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 708DE20936; Fri, 23 Oct 2020 10:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603448297; bh=BV1tH2U1Lsosw+Ugkhs7glTIjtqVDoAJop9TuiKHT44=; h=From:To:Cc:Subject:Date:From; b=FXVNjYYNeEGZSvIhl4SuHitDKUsn6hlGW8Wg42BMzw7N0bBGFCQQcXhfA83VUXfh9 PWbmy5NXe2PNDWiHSzBy2/Ktf60A1UV7UDxoKHO6LjuY2r1O41pscRE2LB20gp4Wkb MSAAeYE9mUg2sG/WR0ot+g2CIOxzKRiblzgHdqDM= From: guoren@kernel.org To: palmerdabbelt@google.com, paul.walmsley@sifive.com, anup@brainfault.org, greentime.hu@sifive.com, zong.li@sifive.com, atish.patra@wdc.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, wesley@sifive.com, yash.shah@sifive.com, hch@lst.de Subject: [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base Date: Fri, 23 Oct 2020 10:17:23 +0000 Message-Id: <1603448245-79429-1-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_061819_022959_1302A770 X-CRM114-Status: GOOD ( 11.92 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, Guo Ren , guoren@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren ENABLE and CONTEXT registers contain M & S status for per-hart, so ref to the specification the correct definition is double to the current value. The value of hart_base and enable_base should be calculated by real physical hartid not software id. Sometimes the CPU node's from dts is not equal to the sequence index. Signed-off-by: Guo Ren --- drivers/irqchip/irq-sifive-plic.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index eaa3e9f..2e56576 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -44,16 +44,16 @@ * Each hart context has a vector of interrupt enable bits associated with it. * There's one bit for each interrupt source. */ -#define ENABLE_BASE 0x2000 -#define ENABLE_PER_HART 0x80 +#define ENABLE_BASE 0x2080 +#define ENABLE_PER_HART 0x100 /* * Each hart context has a set of control registers associated with it. Right * now there's only two: a source priority threshold over which the hart will * take an interrupt, and a register to claim interrupts. */ -#define CONTEXT_BASE 0x200000 -#define CONTEXT_PER_HART 0x1000 +#define CONTEXT_BASE 0x201000 +#define CONTEXT_PER_HART 0x2000 #define CONTEXT_THRESHOLD 0x00 #define CONTEXT_CLAIM 0x04 @@ -358,10 +358,10 @@ static int __init plic_init(struct device_node *node, cpumask_set_cpu(cpu, &priv->lmask); handler->present = true; handler->hart_base = - priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART; + priv->regs + CONTEXT_BASE + hartid * CONTEXT_PER_HART; raw_spin_lock_init(&handler->enable_lock); handler->enable_base = - priv->regs + ENABLE_BASE + i * ENABLE_PER_HART; + priv->regs + ENABLE_BASE + hartid * ENABLE_PER_HART; handler->priv = priv; done: for (hwirq = 1; hwirq <= nr_irqs; hwirq++)