From patchwork Sun Jun 6 09:04:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12301943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D6CDC48BC2 for ; Sun, 6 Jun 2021 09:05:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 37D0361422 for ; Sun, 6 Jun 2021 09:05:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 37D0361422 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Hq6RsR2Swq9fGxQqkls/dzFAiBb/qjwM66RSLnWdqBc=; b=xwEgjc3NjKr0yL 9oqwfhQh/lt7B0dB0igONU6a7FZiY9c+RsOsNqr4JajMeYyrDs/8gy0kPn3G3imeSD7DDepDcEEvB +yPR+tmeL/BeMGO6Nrdwub0xrqz7NGru4uX1DMWYSkDi7KqKkW/OKc87rPtPaKvr/90/fOHo/Guul 1N+gOrO+ZAXOdmZJGO4PIpSniPTfR0MVb3Lb1EYPxR1wysSWEj9/1IKVO4g38OHE5YjXucfTMqw+B Yd8345psBnqcW2RQN4Pb/rs6RKkQb+qUBFKmQu0S3aGmf1z4CDcxNLArA3f8jF1ZxbREQ9VKetuwA BzXsDAyOLZCnWt6HyZHA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lpois-0002mR-0E; Sun, 06 Jun 2021 09:05:34 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lpoip-0002kj-3N for linux-riscv@lists.infradead.org; Sun, 06 Jun 2021 09:05:32 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id D5DFC61445; Sun, 6 Jun 2021 09:05:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1622970330; bh=ImFn70PLgXUHSxXz/kYrTQSzz2TKvLSmtoIrB/isbsc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oTU1FSyzc5fcybOhyi+u8t+br3DWkuLwmupadD/Yomq3S6+lWcUikjVV54ATWVgn+ redgdfL7kRxmeHtrDf3J/PkBf+SqRJU9OUPkBFZ88JpuSsmzZqBnEC5vtCwbVmdLOT RMzGI8bHicLzQIoIa94hBcAaXqONFnEQyBNccAc3ANs3YUdXsL7H8goFtTvcOKSzri 9390z8bnrXbtNFVMGsY109+L44AgY15cyXeVXb7i/a/J3EgrsNWSUyAzEbFb4N9ulU dahA1uihDqbh3Fowr4I81ebUEkwGMDwh6moZDYEx50U+1RCA07yU1HaPBt1/P23bsu zjul+x/c5bT9A== From: guoren@kernel.org To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, drew@beagleboard.org, liush@allwinnertech.com, lazyparser@gmail.com, wefu@redhat.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren , Christoph Hellwig Subject: [RFC PATCH v2 06/11] riscv: pgtable: Add DMA_COHERENT with custom PTE attributes Date: Sun, 6 Jun 2021 09:04:04 +0000 Message-Id: <1622970249-50770-10-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622970249-50770-1-git-send-email-guoren@kernel.org> References: <1622970249-50770-1-git-send-email-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210606_020531_203886_E7AB7F3A X-CRM114-Status: GOOD ( 17.34 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The dma-noncoherent SOCs need different virtual memory mappings with different attributes: - noncached + Strong Order (for IO/DMA descriptor) - noncached + Weak Order (for writecombine usage, eg: frame buffer) All above base on PTE attributes by MMU hardware. That means address attributes are determined by PTE entry, not PMA. RISC-V soc vendors have defined their own custom PTE attributes for dma-noncoherency. Signed-off-by: Guo Ren Signed-off-by: Liu Shaohua Cc: Palmer Dabbelt Cc: Christoph Hellwig Cc: Anup Patel Cc: Arnd Bergmann Cc: Drew Fustini Cc: Wei Fu Cc: Wei Wu Cc: Chen-Yu Tsai Cc: Maxime Ripard --- arch/riscv/include/asm/pgtable-bits.h | 20 +++++++++++++++++++- arch/riscv/include/asm/pgtable.h | 11 ++++------- arch/riscv/include/asm/soc.h | 1 + arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/soc.c | 22 ++++++++++++++++++++++ arch/riscv/mm/init.c | 4 ++++ 6 files changed, 51 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index bbaeb5d..080a9eb 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -24,6 +24,11 @@ #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */ #define _PAGE_SOFT (1 << 8) /* Reserved for software */ +#define _PAGE_DMA_MASK __riscv_custom_pte.mask +#define _PAGE_DMA_CACHE __riscv_custom_pte.cache +#define _PAGE_DMA_IO __riscv_custom_pte.io +#define _PAGE_DMA_WC __riscv_custom_pte.wc + #define _PAGE_SPECIAL _PAGE_SOFT #define _PAGE_TABLE _PAGE_PRESENT @@ -35,9 +40,22 @@ #define _PAGE_PFN_SHIFT 10 +#ifndef __ASSEMBLY__ + +struct riscv_custom_pte { + unsigned long cache; + unsigned long mask; + unsigned long io; + unsigned long wc; +}; + +extern struct riscv_custom_pte __riscv_custom_pte; + /* Set of bits to preserve across pte_modify() */ #define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ _PAGE_WRITE | _PAGE_EXEC | \ - _PAGE_USER | _PAGE_GLOBAL)) + _PAGE_USER | _PAGE_GLOBAL | \ + _PAGE_DMA_MASK)) +#endif #endif /* _ASM_RISCV_PGTABLE_BITS_H */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 13a79643..6ddeb49 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -114,7 +114,7 @@ #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) /* Page protection bits */ -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) +#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER | _PAGE_DMA_CACHE) #define PAGE_NONE __pgprot(_PAGE_PROT_NONE) #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) @@ -135,7 +135,8 @@ | _PAGE_PRESENT \ | _PAGE_ACCESSED \ | _PAGE_DIRTY \ - | _PAGE_GLOBAL) + | _PAGE_GLOBAL \ + | _PAGE_DMA_CACHE) #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) @@ -145,11 +146,7 @@ #define PAGE_TABLE __pgprot(_PAGE_TABLE) -/* - * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't - * change the properties of memory regions. - */ -#define _PAGE_IOREMAP _PAGE_KERNEL +#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_DMA_MASK) | _PAGE_DMA_IO) extern pgd_t swapper_pg_dir[]; diff --git a/arch/riscv/include/asm/soc.h b/arch/riscv/include/asm/soc.h index f494066..fc587d7 100644 --- a/arch/riscv/include/asm/soc.h +++ b/arch/riscv/include/asm/soc.h @@ -17,6 +17,7 @@ = { .compatible = compat, .data = fn } void soc_early_init(void); +void soc_setup_vm(void); extern unsigned long __soc_early_init_table_start; extern unsigned long __soc_early_init_table_end; diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index 9d93421..c2710f3 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -6,5 +6,6 @@ #define ASM_VENDOR_LIST_H #define SIFIVE_VENDOR_ID 0x489 +#define THEAD_VENDOR_ID 0x401 #endif diff --git a/arch/riscv/kernel/soc.c b/arch/riscv/kernel/soc.c index a051617..05fa764 100644 --- a/arch/riscv/kernel/soc.c +++ b/arch/riscv/kernel/soc.c @@ -3,8 +3,10 @@ * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include +#include #include #include +#include #include /* @@ -26,3 +28,23 @@ void __init soc_early_init(void) } } } + +static void __init thead_init(void) +{ + __riscv_custom_pte.cache = 0x7000000000000000; + __riscv_custom_pte.mask = 0xf800000000000000; + __riscv_custom_pte.io = BIT(63); + __riscv_custom_pte.wc = 0; +} + +void __init soc_setup_vm(void) +{ + unsigned long vendor_id = + ((struct riscv_image_header *)(&_start))->res1; + + switch (vendor_id) { + case THEAD_VENDOR_ID: + thead_init(); + break; + } +}; diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 4b398c6..fb70c49 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -524,6 +524,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) pmd_t fix_bmap_spmd, fix_bmap_epmd; #endif + soc_setup_vm(); setup_protection_map(); #ifdef CONFIG_XIP_KERNEL @@ -911,3 +912,6 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, return vmemmap_populate_basepages(start, end, node, NULL); } #endif + +struct riscv_custom_pte __riscv_custom_pte __ro_after_init; +EXPORT_SYMBOL(__riscv_custom_pte);