diff mbox series

[1/5] riscv: __asm_to/copy_from_user: delete existing code

Message ID 1b454390-cee5-a414-509b-3adb25ec0330@gmail.com (mailing list archive)
State New
Headers show
Series riscv: improving uaccess with logs from network bench | expand

Commit Message

Akira Tsukamoto June 19, 2021, 11:34 a.m. UTC
This is to make the diff easier to read, since the diff on
assembler is horrible to read.

Signed-off-by: Akira Tsukamoto <akira.tsukamoto@gmail.com>
---
 arch/riscv/lib/uaccess.S | 40 ----------------------------------------
 1 file changed, 40 deletions(-)

Comments

David Laight June 21, 2021, 11:45 a.m. UTC | #1
From: Akira Tsukamoto
> Sent: 19 June 2021 12:35
> 
> This is to make the diff easier to read, since the diff on
> assembler is horrible to read.

You can't do that, it breaks bisection.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
Akira Tsukamoto June 21, 2021, 1:55 p.m. UTC | #2
On 6/21/2021 8:45 PM, David Laight wrote:
> From: Akira Tsukamoto
>> Sent: 19 June 2021 12:35
>>
>> This is to make the diff easier to read, since the diff on
>> assembler is horrible to read.
> 
> You can't do that, it breaks bisection.

I know, it is intentional, I explained it on the other thread 
with Ben Dooks.
I just focusing make it easier to be understood of what the
code does right now.

Akira
diff mbox series

Patch

diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
index fceaeb18cc64..da9536e1e9cb 100644
--- a/arch/riscv/lib/uaccess.S
+++ b/arch/riscv/lib/uaccess.S
@@ -19,50 +19,10 @@  ENTRY(__asm_copy_from_user)
 	li t6, SR_SUM
 	csrs CSR_STATUS, t6
 
-	add a3, a1, a2
-	/* Use word-oriented copy only if low-order bits match */
-	andi t0, a0, SZREG-1
-	andi t1, a1, SZREG-1
-	bne t0, t1, 2f
-
-	addi t0, a1, SZREG-1
-	andi t1, a3, ~(SZREG-1)
-	andi t0, t0, ~(SZREG-1)
-	/*
-	 * a3: terminal address of source region
-	 * t0: lowest XLEN-aligned address in source
-	 * t1: highest XLEN-aligned address in source
-	 */
-	bgeu t0, t1, 2f
-	bltu a1, t0, 4f
-1:
-	fixup REG_L, t2, (a1), 10f
-	fixup REG_S, t2, (a0), 10f
-	addi a1, a1, SZREG
-	addi a0, a0, SZREG
-	bltu a1, t1, 1b
-2:
-	bltu a1, a3, 5f
-
-3:
 	/* Disable access to user memory */
 	csrc CSR_STATUS, t6
 	li a0, 0
 	ret
-4: /* Edge case: unalignment */
-	fixup lbu, t2, (a1), 10f
-	fixup sb, t2, (a0), 10f
-	addi a1, a1, 1
-	addi a0, a0, 1
-	bltu a1, t0, 4b
-	j 1b
-5: /* Edge case: remainder */
-	fixup lbu, t2, (a1), 10f
-	fixup sb, t2, (a0), 10f
-	addi a1, a1, 1
-	addi a0, a0, 1
-	bltu a1, a3, 5b
-	j 3b
 ENDPROC(__asm_copy_to_user)
 ENDPROC(__asm_copy_from_user)
 EXPORT_SYMBOL(__asm_copy_to_user)