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Tue, 04 Dec 2018 06:11:20 -0800 (PST) From: Anup Patel To: Greg Kroah-Hartman , Jiri Slaby , Palmer Dabbelt , Albert Ou Subject: [PATCH 2/3] RISC-V: defconfig: Enable RISC-V SBI earlycon support Date: Tue, 4 Dec 2018 19:25:06 +0530 Message-Id: <20181204135507.3706-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181204135507.3706-1-anup@brainfault.org> References: <20181204135507.3706-1-anup@brainfault.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181204_061132_418034_CFE1A185 X-CRM114-Status: GOOD ( 10.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Anup Patel , linux-kernel@vger.kernel.org, Christoph Hellwig , Atish Patra , linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch enables RISC-V SBI earlycon support in default defconfig so that we can use "earlycon=sbi" in kernel parameters for early debug prints. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ef4f15df9adf..f399659d3b8d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -46,6 +46,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_DRM=y