| Message ID | 20190425055015.45487-3-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Allow accessing CSR using CSR number | expand |
> +#ifdef CONFIG_64BIT > +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) > +#else > +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) > +#endif Please keep the existing defintion that doesn't need an ifdef..
On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig <hch@infradead.org> wrote: > > > +#ifdef CONFIG_64BIT > > +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) > > +#else > > +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) > > +#endif > > Please keep the existing defintion that doesn't need an ifdef.. Sure, will do. Regards, Anup
On Thu, Apr 25, 2019 at 12:46:52PM +0530, Anup Patel wrote: > On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig <hch@infradead.org> wrote: > > > > > +#ifdef CONFIG_64BIT > > > +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) > > > +#else > > > +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) > > > +#endif > > > > Please keep the existing defintion that doesn't need an ifdef.. > > Sure, will do. While we're at it: I don't think we need both INTERRUPT_CAUSE_FLAG and SCAUSE_IRQ_FLAG.
On Thu, Apr 25, 2019 at 1:31 PM Christoph Hellwig <hch@infradead.org> wrote: > > On Thu, Apr 25, 2019 at 12:46:52PM +0530, Anup Patel wrote: > > On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig <hch@infradead.org> wrote: > > > > > > > +#ifdef CONFIG_64BIT > > > > +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) > > > > +#else > > > > +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) > > > > +#endif > > > > > > Please keep the existing defintion that doesn't need an ifdef.. > > > > Sure, will do. > > While we're at it: I don't think we need both INTERRUPT_CAUSE_FLAG and > SCAUSE_IRQ_FLAG. Oops, I already send v5. Saw your comment just now. Regards, Anup
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2ae54a7386f1..ab40a936cb2d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -51,10 +51,22 @@ #define SATP_MODE SATP_MODE_39 #endif -/* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ +/* SCAUSE */ +#ifdef CONFIG_64BIT +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) +#else +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) +#endif + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_M_EXT 11 #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1 @@ -66,6 +78,11 @@ #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ +#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) +#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) +#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 48e6b7db83a1..8b7feb94aeb8 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -14,9 +14,9 @@ /* * Possible interrupt causes: */ -#define INTERRUPT_CAUSE_SOFTWARE 1 -#define INTERRUPT_CAUSE_TIMER 5 -#define INTERRUPT_CAUSE_EXTERNAL 9 +#define INTERRUPT_CAUSE_SOFTWARE IRQ_S_SOFT +#define INTERRUPT_CAUSE_TIMER IRQ_S_TIMER +#define INTERRUPT_CAUSE_EXTERNAL IRQ_S_EXT /* * The high order bit of the trap cause register is always set for @@ -24,7 +24,7 @@ * quickly. The INTERRUPT_CAUSE_* macros don't contain that bit, so we * need to mask it off. */ -#define INTERRUPT_CAUSE_FLAG (1UL << (__riscv_xlen - 1)) +#define INTERRUPT_CAUSE_FLAG SCAUSE_IRQ_FLAG int arch_show_interrupts(struct seq_file *p, int prec) {
This patch adds SCAUSE interrupt flag and SCAUSE interrupt related defines to asm/csr.h. We also use these defines in kernel/irq.c and express SIE/SIP flags in-terms of SCAUSE interrupt causes. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 25 +++++++++++++++++++++---- arch/riscv/kernel/irq.c | 8 ++++---- 2 files changed, 25 insertions(+), 8 deletions(-)