From patchwork Mon Aug 5 13:44:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11076989 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E3691399 for ; Mon, 5 Aug 2019 13:44:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EFA072887D for ; Mon, 5 Aug 2019 13:44:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E368128922; Mon, 5 Aug 2019 13:44:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 472832887D for ; Mon, 5 Aug 2019 13:44:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0xtaO1fxWr4428TdPeCpuZJldZ9yhPe/J/p4GWiO3Ms=; b=QsIT0mB24J5eck IK+ex6CNx3QzcEZrFgyQ7Pk4WzLgqJ5jyFyrZQOj62ihO38IYViwX13LmJhKrrqqsuO/BSG1Yxtxk 19BK6nS479Cu4GLlZbBlwgh5S0qUXSs0tNtu55lFbHFWpCzAVPpnVH0VPatfHDDufCOxKTRYeBdRU 6JV/7yUiKqK45oIvhVbHWScKHjNT4dNh+/M8TXywRNejNzVyf8ieq6dtj6v/jGjTi6z8x2B+QddCn l0+HxZ/MOkbt1XDXctJRhBpCuIRNxMxEd14K3I/Fsc5XSnMmeUGJAKYol3MBcWCVG/F/+M6qcGvLh CSZEVxCTH9F+idmR859g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hudHX-0002Um-PC; Mon, 05 Aug 2019 13:44:11 +0000 Received: from esa1.hgst.iphmx.com ([68.232.141.245]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hudHT-0002SJ-0u for linux-riscv@lists.infradead.org; Mon, 05 Aug 2019 13:44:10 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1565012647; x=1596548647; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=rYqdqmbhyParRf1rxKTJipYcEMdVmlpMM4qaFK3AdsI=; b=JKmq+uxxc1GQG2CfgU3ZDl24f/qGjfA+oaV8mDDb/yn8/qbW7SOSVcdb 9Te7AeJrimMmTy4AWrSJqqFtHBGV6pc0eExhJfCyzhJMR5jVuUs4EgGfo lJ17/4JgxvDcz55ZDwDceijFOeQNRZ8ODtmaFBp0Ul2/TqMrjTJiuzBpJ vY/2fGDXr2yvJYXaZ/fJuZjcOvp4X2b/GKPL50EB8uAIsh0wRFZWbq1fc SBWYdXthnGjoqHd9IeZVMWSqofTbuWlbRfXz4JZHitEsEUDl/d9pRf9XV dQketjcnxPEn7LarkEJcGixkGbNpASP+cObi6fHCzohOo25Bg+41Ft4je A==; IronPort-SDR: Syh3bpPmL0PYE8CJo5fZub0erLrUrtPmJ1dRSte0S4RFS1Yl6wjvjlzEaUrwATLkiQW9g+wYSz 6HFEjzX/HZVY+iKQy/co6+39xliC8X1fYHf0QVgpb3wt28n09QLJKBC5bMhp9PmRtyH1H8DTLp 41Um92pP8Wus/oFevtSy6ANtTS3hOkaflvYYB6vw4xz8uuDMAcmZne1pShqCpEfyUfdKdK+KIy t437EFA4+Bg2holJEXODL64y6PsfmXAyLJDAWa9+bzlCH54csidei7Lsl79+yCWMZoaJYUoCoh MWY= X-IronPort-AV: E=Sophos;i="5.64,350,1559491200"; d="scan'208";a="221493506" Received: from mail-sn1nam01lp2054.outbound.protection.outlook.com (HELO NAM01-SN1-obe.outbound.protection.outlook.com) ([104.47.32.54]) by ob1.hgst.iphmx.com with ESMTP; 05 Aug 2019 21:44:05 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=L6hE68Su/nLiRyNygRrZgtsyb4f/HvWYsRH9Fo/LE02V8UikownFDggKDOZSOclOKCzGzt7DBxNEa9bUrgvbFOpmv5n8eAeSpvWKhmdtD/vg2OUccjiTbJArYVBWQtIzYdwN9DCHVcu9yCFf6UTf4Ev4Tk79qek0DniZKVgIo6c/ueOPpLDpF2UXwVBHr7TOfaJNVl484x9vh5hZrkXmkGbIHtMLgHwmk7dI09xCanRY7sr8PyaqcvMr2Uzgg9MhH3whuWjT5KDQji4XGW0Cu2TXwRBDJovEiGfyMtnnExurszERzMm/JM28mec77S6ym600rI7rnSXvl6osOcePmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SncVMPGIQmheGw4JwKgUVwVW86o02vHhw8i+MhdGPeM=; b=oABtqWLIT3ZBXvUv2S+OFncGj7LCXpX+TxPAUybExP2okL4X77Xb5CNNMxxOPlAEG+A8ZU3z9D9DUhxCml1JLq8tI6r9xlZfCjZOPMnJBWvUjXS465mzkcAEqg//HM5fr0NOIj35X8CZWxo3mZNYON/+Hipby2Bwz34NhUdxsm99OT4aHrbQpiNTLTlWFMvfhjcYsR5W3HLiCJwNT57Y76Sm3GATxVOS/QD8OeDBmYOaJ+oDTe62m8RZDdVzJoOAfCMtFqqK1sL/tsEaAVbE6iP8fqy5X0fnMKFLVKjuya5T8FKWBLumlr9yKXsTJE2hD+Hkpy0RIiAxyMrZm6Cb1A== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=wdc.com;dmarc=pass action=none header.from=wdc.com;dkim=pass header.d=wdc.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SncVMPGIQmheGw4JwKgUVwVW86o02vHhw8i+MhdGPeM=; b=xyqTGLQpGW+fs1pGTpPBLMr24g9mWICDb2WoG6f4FV4Xo3YpJ1sVUNHAIJnJcXtwBN2uZ3mAaX9Q+fjQYfmY+yYtBYse4pz9lmUlTnxbEIk0Aks44DnGJs+gZuQODV5JBUdXSthqeWH/2XAxN/g9k+ipBb53Rw3s2Oe8n8o8Tnc= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6159.namprd04.prod.outlook.com (20.178.249.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2136.17; Mon, 5 Aug 2019 13:44:04 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::a815:e61a:b4aa:60c8]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::a815:e61a:b4aa:60c8%7]) with mapi id 15.20.2136.018; Mon, 5 Aug 2019 13:44:04 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v3 14/19] RISC-V: KVM: Add timer functionality Thread-Topic: [PATCH v3 14/19] RISC-V: KVM: Add timer functionality Thread-Index: AQHVS5PYt0OBGR24YU2ojAYLq9YdDg== Date: Mon, 5 Aug 2019 13:44:03 +0000 Message-ID: <20190805134201.2814-15-anup.patel@wdc.com> References: <20190805134201.2814-1-anup.patel@wdc.com> In-Reply-To: <20190805134201.2814-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0087.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:54::27) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [106.51.20.197] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8d90169f-0b3c-4a4a-b431-08d719aafaa9 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:MN2PR04MB6159; x-ms-traffictypediagnostic: MN2PR04MB6159: x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:6108; x-forefront-prvs: 01208B1E18 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(39860400002)(136003)(366004)(396003)(376002)(346002)(189003)(199004)(66556008)(66476007)(71190400001)(71200400001)(110136005)(54906003)(66946007)(66446008)(64756008)(86362001)(5660300002)(102836004)(52116002)(55236004)(14454004)(99286004)(386003)(78486014)(316002)(256004)(14444005)(6506007)(76176011)(2616005)(6486002)(8676002)(9456002)(8936002)(36756003)(3846002)(6116002)(6512007)(4326008)(2906002)(476003)(305945005)(44832011)(81156014)(81166006)(26005)(186003)(486006)(11346002)(25786009)(7736002)(1076003)(50226002)(478600001)(68736007)(446003)(53936002)(66066001)(6436002)(7416002); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6159; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: lpe/tlR4zLLrWZtOP4On+SsmwoowYSzFm2upy2meXS0eczk1rMAvdkk8gDOF2WygTwU10dhC7xJY7vfXGgf4dGBTSiDlkRg8epCLuQoH21YGtHi5Rev5zGpgY43yQ8m/5U2/9HT6gDlVrZ/GciF+RWL+M3GuQsyH5isjqXuc7dbCTDfJPJnDKIXJih5hAjq8fsuha6qvE5ztZwcmHlcNw/3U4kdAoQrZgYOfkBszYoqum9xdNaC6LUhbxi4X0KE88wkFzlUjG/0idn2Lw7eeV4FBCPs8omxJjrlCT50bNw6kopGYB/q8PxZ09EX2wJJlLqHNu2nrMdvZMs4/Bfke3A81kRwvCH0rz7nDrsQR3cGeDiAABIRQC4uGEEEqUQnI7gomnhMc7DOM4Tow9ik+v8xeAMqhqsZYme1N5BamGUE= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8d90169f-0b3c-4a4a-b431-08d719aafaa9 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2019 13:44:03.9543 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6159 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190805_064408_500905_EEC32899 X-CRM114-Status: GOOD ( 21.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Atish Patra The RISC-V hypervisor specification doesn't have any virtual timer feature. Due to this, the guest VCPU timer will be programmed via SBI calls. The host will use a separate hrtimer event for each guest VCPU to provide timer functionality. We inject a virtual timer interrupt to the guest VCPU whenever the guest VCPU hrtimer event expires. The following features are not supported yet and will be added in future: 1. A time offset to adjust guest time from host time 2. A saved next event in guest vcpu for vm migration Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_timer.h | 32 +++++++ arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu.c | 6 ++ arch/riscv/kvm/vcpu_timer.c | 106 ++++++++++++++++++++++++ drivers/clocksource/timer-riscv.c | 8 ++ include/clocksource/timer-riscv.h | 16 ++++ 7 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_timer.h create mode 100644 arch/riscv/kvm/vcpu_timer.c create mode 100644 include/clocksource/timer-riscv.h diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index d6ee69023a83..cd43618461fd 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_64BIT #define KVM_MAX_VCPUS (1U << 16) @@ -167,6 +168,9 @@ struct kvm_vcpu_arch { unsigned long irqs_pending; unsigned long irqs_pending_mask; + /* VCPU Timer */ + struct kvm_vcpu_timer timer; + /* MMIO instruction details */ struct kvm_mmio_decode mmio_decode; diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h new file mode 100644 index 000000000000..df67ea86988e --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __KVM_VCPU_RISCV_TIMER_H +#define __KVM_VCPU_RISCV_TIMER_H + +#include + +#define VCPU_TIMER_PROGRAM_THRESHOLD_NS 1000 + +struct kvm_vcpu_timer { + bool init_done; + /* Check if the timer is programmed */ + bool is_set; + struct hrtimer hrt; + /* Mult & Shift values to get nanosec from cycles */ + u32 mult; + u32 shift; +}; + +int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, + unsigned long ncycles); + +#endif diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index c0f57f26c13d..3e0c7558320d 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -9,6 +9,6 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) kvm-objs += main.o vm.o vmid.o tlb.o mmu.o -kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 1cba8d3af63a..b78ac2aecca2 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -53,6 +53,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) memcpy(cntx, reset_cntx, sizeof(*cntx)); + kvm_riscv_vcpu_timer_reset(vcpu); + WRITE_ONCE(vcpu->arch.irqs_pending, 0); WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); } @@ -107,6 +109,9 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_SP2P; cntx->hstatus |= HSTATUS_SPV; + /* Setup VCPU timer */ + kvm_riscv_vcpu_timer_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); @@ -115,6 +120,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { + kvm_riscv_vcpu_timer_deinit(vcpu); kvm_riscv_stage2_flush_cache(vcpu); kmem_cache_free(kvm_vcpu_cache, vcpu); } diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c new file mode 100644 index 000000000000..a45ca06e1aa6 --- /dev/null +++ b/arch/riscv/kvm/vcpu_timer.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include + +static enum hrtimer_restart kvm_riscv_vcpu_hrtimer_expired(struct hrtimer *h) +{ + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer); + + t->is_set = false; + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_TIMER); + + return HRTIMER_NORESTART; +} + +static u64 kvm_riscv_delta_cycles2ns(u64 cycles, struct kvm_vcpu_timer *t) +{ + unsigned long flags; + u64 cycles_now, cycles_delta, delta_ns; + + local_irq_save(flags); + cycles_now = get_cycles64(); + if (cycles_now < cycles) + cycles_delta = cycles - cycles_now; + else + cycles_delta = 0; + delta_ns = (cycles_delta * t->mult) >> t->shift; + local_irq_restore(flags); + + return delta_ns; +} + +static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) +{ + if (!t->init_done || !t->is_set) + return -EINVAL; + + hrtimer_cancel(&t->hrt); + t->is_set = false; + + return 0; +} + +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, + unsigned long ncycles) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + u64 delta_ns = kvm_riscv_delta_cycles2ns(ncycles, t); + + if (!t->init_done) + return -EINVAL; + + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_TIMER); + + if (delta_ns > VCPU_TIMER_PROGRAM_THRESHOLD_NS) { + hrtimer_start(&t->hrt, ktime_add_ns(ktime_get(), delta_ns), + HRTIMER_MODE_ABS); + t->is_set = true; + } else + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_TIMER); + + return 0; +} + +int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + if (t->init_done) + return -EINVAL; + + hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; + t->init_done = true; + t->is_set = false; + + riscv_cs_get_mult_shift(&t->mult, &t->shift); + + return 0; +} + +int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu) +{ + int ret; + + ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); + vcpu->arch.timer.init_done = false; + + return ret; +} + +int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) +{ + return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); +} diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 09e031176bc6..7c595203aa5c 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +81,13 @@ static int riscv_timer_dying_cpu(unsigned int cpu) return 0; } +void riscv_cs_get_mult_shift(u32 *mult, u32 *shift) +{ + *mult = riscv_clocksource.mult; + *shift = riscv_clocksource.shift; +} +EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift); + /* called directly from the low-level interrupt handler */ void riscv_timer_interrupt(void) { diff --git a/include/clocksource/timer-riscv.h b/include/clocksource/timer-riscv.h new file mode 100644 index 000000000000..e94e4feecbe8 --- /dev/null +++ b/include/clocksource/timer-riscv.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __TIMER_RISCV_H +#define __TIMER_RISCV_H + +#include + +void riscv_cs_get_mult_shift(u32 *mult, u32 *shift); + +#endif