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[203.116.164.13]) by smtp.gmail.com with ESMTPSA id z12sm47192310pfj.41.2019.09.13.12.27.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2019 12:27:42 -0700 (PDT) Subject: [PATCH 1/4] Documentation: riscv: boot: We're not compatible with arm64 Date: Fri, 13 Sep 2019 12:24:30 -0700 Message-Id: <20190913192433.4316-2-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190913192433.4316-1-palmer@sifive.com> References: <20190913192433.4316-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: linux-riscv@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190913_122744_264972_5B7B5245 X-CRM114-Status: GOOD ( 10.75 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [209.85.214.196 listed in list.dnswl.org] 0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.214.196 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org The documentation for our bootloader claims that it can be made compatible with arm64, but that's not true. There are some differences between our format and arm64: * We've used the first 32 bits of their 64-bit "res2" as a version number, which we're currently setting to non-zero. * We're using their "res4" field as our magic number. * We're treating their magic number as our "res3" field, which nominally contains a flag for big endian systems already. This can't get set, so we should just drop it -- it's also not described what the flag means. This patch removes the claim that our header can be made compatible with arm64. Signed-off-by: Palmer Dabbelt --- Documentation/riscv/boot-image-header.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/riscv/boot-image-header.txt b/Documentation/riscv/boot-image-header.txt index 1b73fea23b39..77e8e505bc41 100644 --- a/Documentation/riscv/boot-image-header.txt +++ b/Documentation/riscv/boot-image-header.txt @@ -21,9 +21,8 @@ The following 64-byte header is present in decompressed Linux kernel image. u32 res3; /* Reserved for additional RISC-V specific header */ u32 res4; /* Reserved for PE COFF offset */ -This header format is compliant with PE/COFF header and largely inspired from -ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common -header in future. +This header format is compliant with PE/COFF header and largely inspired by, +but not compatible with, the ARM64 header. Notes: - This header can also be reused to support EFI stub for RISC-V in future. EFI