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18 Nov 2019 14:52:19 -0800 IronPort-SDR: ORHKxrkZNmOAAk3pK3OLRdWFogOk5FChZF2KqD1suGAmeo6KkAAxmcain2T9LpS+qzh7Lt3Bww wblaxNVjpdEYDaZpWBLXidK6W8o+GdlbF3xXCmZ3AJw4ONHgBurYnUQwQszRVzaRSNokzwadtg RNTKaB4zSqL57k9FgYVtbieyr0ixbcjv0hRuEvrTfR+YmfHJZI9YVeOFvAAu9Qh3KW5RQM959K sWu+n9H6Cim/nmmvCi4CsABsUsIe0faHBK0PFz/6/1Kepjx7wjU/tU2EySX/uHNDK8P82N7T+N IvY= WDCIronportException: Internal Received: from yoda.sdcorp.global.sandisk.com (HELO yoda.int.fusionio.com) ([10.196.158.237]) by uls-op-cesaip02.wdc.com with ESMTP; 18 Nov 2019 14:57:07 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] RISC-V: Introduce a new config for SBI v0.1 Date: Mon, 18 Nov 2019 14:45:38 -0800 Message-Id: <20191118224539.2171-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118224539.2171-1-atish.patra@wdc.com> References: <20191118224539.2171-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191118_145715_625552_31F4824A X-CRM114-Status: GOOD ( 10.23 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.153.144 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Alexios Zavras , Anup Patel , Mike Rapoport , Atish Patra , Jonathan Behrens , Palmer Dabbelt , Mao Han , Gary Guo , Paul Walmsley , linux-riscv@lists.infradead.org, Christoph Hellwig , Allison Randal Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org We now have SBI v0.2 which is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. Introduce a new config and move all SBI v0.1 code under that config. This allows to implement the new replacement SBI extensions cleanly and remove v0.1 extensions easily in future. Currently, the config is enabled by default. Once all M-mode software with v0.1 are no longer in use, this config option and all relevant code can be easily removed. Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 6 ++++ arch/riscv/kernel/sbi.c | 69 +++++++++++++++++++++++++++++------------ 2 files changed, 55 insertions(+), 20 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8eebbc8860bb..4881b87d0d14 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -272,6 +272,12 @@ menu "Kernel features" source "kernel/Kconfig.hz" +config RISCV_SBI_V01 + bool "SBI v0.1 support" + default y + help + This config allows kernel to use SBI v0.1 APIs. This will be + deprecated in future once legacy M-mode software are no longer in use. endmenu menu "Boot options" diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 1cee3ef009bb..6c864fd7fb95 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -52,6 +52,7 @@ int sbi_err_map_linux_errno(int err) }; } +#ifdef CONFIG_RISCV_SBI_V01 /** * sbi_console_putchar() - Writes given character to the console device. * @ch: The data to be written to the console. @@ -78,39 +79,47 @@ int sbi_console_getchar(void) } /** - * sbi_set_timer() - Program the timer for next timer event. - * @stime_value: The value after which next timer event should fire. + * sbi_shutdown() - Remove all the harts from executing supervisor code. * * Return: None */ -void sbi_set_timer(uint64_t stime_value) +void sbi_shutdown(void) { -#if __riscv_xlen == 32 - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, - stime_value >> 32, 0, 0, 0, 0); -#else - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); -#endif + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); } /** - * sbi_shutdown() - Remove all the harts from executing supervisor code. + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. * * Return: None */ -void sbi_shutdown(void) +void sbi_clear_ipi(void) { - sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); } +#endif + /** - * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. + * sbi_set_timer() - Program the timer for next timer event. + * @stime_value: The value after which next timer event should fire. * * Return: None */ -void sbi_clear_ipi(void) +void sbi_set_timer(uint64_t stime_value) { - sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); +#ifdef CONFIG_RISCV_SBI_V01 + if (sbi_spec_is_0_1()) { +#if __riscv_xlen == 32 + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, + stime_value >> 32, 0, 0, 0, 0); +#else + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); +#endif + return; + } +#endif + } /** @@ -121,8 +130,13 @@ void sbi_clear_ipi(void) */ void sbi_send_ipi(const unsigned long *hart_mask) { - sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, +#ifdef CONFIG_RISCV_SBI_V01 + if (sbi_spec_is_0_1()) { + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, 0, 0, 0, 0, 0); + return; + } +#endif } /** @@ -133,8 +147,13 @@ void sbi_send_ipi(const unsigned long *hart_mask) */ void sbi_remote_fence_i(const unsigned long *hart_mask) { - sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask, - 0, 0, 0, 0, 0); +#ifdef CONFIG_RISCV_SBI_V01 + if (sbi_spec_is_0_1()) { + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, + (unsigned long)hart_mask, 0, 0, 0, 0, 0); + return; + } +#endif } /** @@ -150,8 +169,13 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size) { - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, +#ifdef CONFIG_RISCV_SBI_V01 + if (sbi_spec_is_0_1()) { + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, (unsigned long)hart_mask, start, size, 0, 0, 0); + return; + } +#endif } /** @@ -170,8 +194,13 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long size, unsigned long asid) { - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, +#ifdef CONFIG_RISCV_SBI_V01 + if (sbi_spec_is_0_1()) { + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, (unsigned long)hart_mask, start, size, asid, 0, 0); + return; + } +#endif } /**