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Tue, 26 Nov 2019 17:46:15 -0500 (EST) From: Marc Gauthier To: linux-riscv@lists.infradead.org Subject: [PATCH v2 2/2] riscv: Set SHMLBA according to cache geometry Date: Tue, 26 Nov 2019 17:44:46 -0500 Message-Id: <20191126224446.15145-3-consult-mg@gstardust.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191126224446.15145-1-consult-mg@gstardust.com> References: <20191126224446.15145-1-consult-mg@gstardust.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191126_144617_022074_49880A9C X-CRM114-Status: GOOD ( 15.16 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [64.147.123.19 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Gauthier , Palmer Dabbelt , Albert Ou , Paul Walmsley MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org Set SHMLBA to the maximum cache "span" (line size * number of sets) of all CPU L1 instruction and data caches (L2 and up are rarely VIPT). This avoids VIPT cache aliasing with minimal alignment constraints. If the device tree does not provide cache parameters, use a conservative default of 16 KB: only large enough to avoid aliasing in most VIPT caches. Signed-off-by: Marc Gauthier --- arch/riscv/include/asm/Kbuild | 1 - arch/riscv/include/asm/shmparam.h | 12 +++++++ arch/riscv/kernel/cacheinfo.c | 52 +++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/shmparam.h diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 16970f246860..3905765807af 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -27,7 +27,6 @@ generic-y += percpu.h generic-y += preempt.h generic-y += sections.h generic-y += serial.h -generic-y += shmparam.h generic-y += topology.h generic-y += trace_clock.h generic-y += unaligned.h diff --git a/arch/riscv/include/asm/shmparam.h b/arch/riscv/include/asm/shmparam.h new file mode 100644 index 000000000000..9b6a98153648 --- /dev/null +++ b/arch/riscv/include/asm/shmparam.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_SHMPARAM_H +#define _ASM_RISCV_SHMPARAM_H + +/* + * Minimum alignment of shared memory segments as a function of cache geometry. + */ +#define SHMLBA arch_shmlba() + +long arch_shmlba(void); + +#endif /* _ASM_RISCV_SHMPARAM_H */ diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 4c90c07d8c39..1bc7df8577d6 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -1,12 +1,61 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2017 SiFive + * Copyright (C) 2019 Aril Inc */ #include #include #include #include +#include + +static long shmlba; + + +/* + * Assuming cache size = line size * #sets * N for N-way associative caches, + * return the max cache "span" == (line size * #sets) == (cache size / N) + * across all L1 caches, or 0 if cache parameters are not available. + * VIPT caches with span > min page size are susceptible to aliasing. + */ +static long get_max_cache_span(void) +{ + struct cpu_cacheinfo *this_cpu_ci; + struct cacheinfo *this_leaf; + long span, max_span = 0; + int cpu, leaf; + + for_each_possible_cpu(cpu) { + this_cpu_ci = get_cpu_cacheinfo(cpu); + this_leaf = this_cpu_ci->info_list; + for (leaf = 0; leaf < this_cpu_ci->num_leaves; leaf++) { + if (this_leaf->level > 1) + break; + span = this_leaf->coherency_line_size * + this_leaf->number_of_sets; + if (span > max_span) + max_span = span; + this_leaf++; + } + } + return max_span; +} + +/* + * Align shared mappings to the maximum cache "span" to avoid aliasing + * in VIPT caches, for performance. + * The returned SHMLBA value is always a power-of-two multiple of PAGE_SIZE. + */ +long arch_shmlba(void) +{ + if (shmlba == 0) { + long max_span = get_max_cache_span(); + + shmlba = max_span ? PAGE_ALIGN(max_span) : 4 * PAGE_SIZE; + } + return shmlba; +} static void ci_leaf_init(struct cacheinfo *this_leaf, struct device_node *node, @@ -93,6 +142,9 @@ static int __populate_cache_leaves(unsigned int cpu) } of_node_put(np); + /* Force recalculating SHMLBA if cache parameters are updated. */ + shmlba = 0; + return 0; }