| Message ID | 20200102030954.41225-1-zong.li@sifive.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | riscv: gcov: enable gcov for RISC-V | expand |
On Thu, Jan 2, 2020 at 8:40 AM Zong Li <zong.li@sifive.com> wrote: > > This patch enables GCOV code coverage measurement on RISC-V. > Lightly tested on QEMU and Hifive Unleashed board, seems to work as > expected. > > Signed-off-by: Zong Li <zong.li@sifive.com> > --- > Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +- > arch/riscv/Kconfig | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt > index 059d58a549c7..6fb2b0671994 100644 > --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt > +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt > @@ -23,7 +23,7 @@ > | openrisc: | TODO | > | parisc: | TODO | > | powerpc: | ok | > - | riscv: | TODO | > + | riscv: | ok | > | s390: | ok | > | sh: | ok | > | sparc: | TODO | > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8efbaa78d67..a31169b02ec0 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -64,6 +64,7 @@ config RISCV > select SPARSEMEM_STATIC if 32BIT > select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU > select HAVE_ARCH_MMAP_RND_BITS if MMU > + select ARCH_HAS_GCOV_PROFILE_ALL > > config ARCH_MMAP_RND_BITS_MIN > default 18 if 64BIT > -- > 2.24.1 > Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> May be (not 100% sure) split this into two patches so that Documentation patch can be taken by Jonathan. Regards, Anup
On Thu, Jan 2, 2020 at 11:37 AM Anup Patel <anup@brainfault.org> wrote: > > On Thu, Jan 2, 2020 at 8:40 AM Zong Li <zong.li@sifive.com> wrote: > > > > This patch enables GCOV code coverage measurement on RISC-V. > > Lightly tested on QEMU and Hifive Unleashed board, seems to work as > > expected. > > > > Signed-off-by: Zong Li <zong.li@sifive.com> > > --- > > Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +- > > arch/riscv/Kconfig | 1 + > > 2 files changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt > > index 059d58a549c7..6fb2b0671994 100644 > > --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt > > +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt > > @@ -23,7 +23,7 @@ > > | openrisc: | TODO | > > | parisc: | TODO | > > | powerpc: | ok | > > - | riscv: | TODO | > > + | riscv: | ok | > > | s390: | ok | > > | sh: | ok | > > | sparc: | TODO | > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index d8efbaa78d67..a31169b02ec0 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -64,6 +64,7 @@ config RISCV > > select SPARSEMEM_STATIC if 32BIT > > select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU > > select HAVE_ARCH_MMAP_RND_BITS if MMU > > + select ARCH_HAS_GCOV_PROFILE_ALL > > > > config ARCH_MMAP_RND_BITS_MIN > > default 18 if 64BIT > > -- > > 2.24.1 > > > > Looks good to me. > > Reviewed-by: Anup Patel <anup@brainfault.org> > > May be (not 100% sure) split this into two patches so that > Documentation patch can be taken by Jonathan. OK, let me split this patch in next version. > > Regards, > Anup
On Thu, 2 Jan 2020 09:07:12 +0530 Anup Patel <anup@brainfault.org> wrote: > May be (not 100% sure) split this into two patches so that > Documentation patch can be taken by Jonathan. That's fine if you want, but this patch can also easily go together through the risc-v tree. Acked-by: Jonathan Corbet <corbet@lwn.net> jon
On Thu, 2 Jan 2020, Zong Li wrote: > This patch enables GCOV code coverage measurement on RISC-V. > Lightly tested on QEMU and Hifive Unleashed board, seems to work as > expected. > > Signed-off-by: Zong Li <zong.li@sifive.com> Thanks, queued for v5.5-rc. - Paul
diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt index 059d58a549c7..6fb2b0671994 100644 --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt @@ -23,7 +23,7 @@ | openrisc: | TODO | | parisc: | TODO | | powerpc: | ok | - | riscv: | TODO | + | riscv: | ok | | s390: | ok | | sh: | ok | | sparc: | TODO | diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d8efbaa78d67..a31169b02ec0 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,7 @@ config RISCV select SPARSEMEM_STATIC if 32BIT select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select HAVE_ARCH_MMAP_RND_BITS if MMU + select ARCH_HAS_GCOV_PROFILE_ALL config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT
This patch enables GCOV code coverage measurement on RISC-V. Lightly tested on QEMU and Hifive Unleashed board, seems to work as expected. Signed-off-by: Zong Li <zong.li@sifive.com> --- Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +- arch/riscv/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)