| Message ID | 20200322110028.18279-7-alex@ghiti.fr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce sv48 support | expand |
+Device tree mailing list On Sun, Mar 22, 2020 at 4:36 PM Alexandre Ghiti <alex@ghiti.fr> wrote: > > This property can not be used before virtual memory is set up > and then the distinction between sv39 and sv48 is done at runtime > using SATP csr property: this property is now useless, so remove it. > > Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 13 ------------- > 1 file changed, 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 04819ad379c2..12baabbac213 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -39,19 +39,6 @@ properties: > Identifies that the hart uses the RISC-V instruction set > and identifies the type of the hart. > > - mmu-type: > - allOf: > - - $ref: "/schemas/types.yaml#/definitions/string" > - - enum: > - - riscv,sv32 > - - riscv,sv39 > - - riscv,sv48 > - description: > - Identifies the MMU address translation mode used on this > - hart. These values originate from the RISC-V Privileged > - Specification document, available from > - https://riscv.org/specifications/ > - > riscv,isa: > allOf: > - $ref: "/schemas/types.yaml#/definitions/string" > -- > 2.20.1 > Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup
On Sun, 22 Mar 2020 04:00:27 PDT (-0700), alex@ghiti.fr wrote: > This property can not be used before virtual memory is set up > and then the distinction between sv39 and sv48 is done at runtime > using SATP csr property: this property is now useless, so remove it. > > Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 13 ------------- > 1 file changed, 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 04819ad379c2..12baabbac213 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -39,19 +39,6 @@ properties: > Identifies that the hart uses the RISC-V instruction set > and identifies the type of the hart. > > - mmu-type: > - allOf: > - - $ref: "/schemas/types.yaml#/definitions/string" > - - enum: > - - riscv,sv32 > - - riscv,sv39 > - - riscv,sv48 > - description: > - Identifies the MMU address translation mode used on this > - hart. These values originate from the RISC-V Privileged > - Specification document, available from > - https://riscv.org/specifications/ > - > riscv,isa: > allOf: > - $ref: "/schemas/types.yaml#/definitions/string" I'd prefer if we continue to define this in the schema: while Linux won't use it, it's still useful for other programs that want to statically determine the available VA widths.
On 4/3/20 11:53 AM, Palmer Dabbelt wrote: > On Sun, 22 Mar 2020 04:00:27 PDT (-0700), alex@ghiti.fr wrote: >> This property can not be used before virtual memory is set up >> and then the distinction between sv39 and sv48 is done at runtime >> using SATP csr property: this property is now useless, so remove it. >> >> Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> >> --- >> Documentation/devicetree/bindings/riscv/cpus.yaml | 13 ------------- >> 1 file changed, 13 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml >> b/Documentation/devicetree/bindings/riscv/cpus.yaml >> index 04819ad379c2..12baabbac213 100644 >> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml >> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml >> @@ -39,19 +39,6 @@ properties: >> Identifies that the hart uses the RISC-V instruction set >> and identifies the type of the hart. >> >> - mmu-type: >> - allOf: >> - - $ref: "/schemas/types.yaml#/definitions/string" >> - - enum: >> - - riscv,sv32 >> - - riscv,sv39 >> - - riscv,sv48 >> - description: >> - Identifies the MMU address translation mode used on this >> - hart. These values originate from the RISC-V Privileged >> - Specification document, available from >> - https://riscv.org/specifications/ >> - >> riscv,isa: >> allOf: >> - $ref: "/schemas/types.yaml#/definitions/string" > > I'd prefer if we continue to define this in the schema: while Linux > won't use > it, it's still useful for other programs that want to statically > determine the > available VA widths. Sure, I'll remove that in next version. Thanks, Alex
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 04819ad379c2..12baabbac213 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,19 +39,6 @@ properties: Identifies that the hart uses the RISC-V instruction set and identifies the type of the hart. - mmu-type: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: - - riscv,sv32 - - riscv,sv39 - - riscv,sv48 - description: - Identifies the MMU address translation mode used on this - hart. These values originate from the RISC-V Privileged - Specification document, available from - https://riscv.org/specifications/ - riscv,isa: allOf: - $ref: "/schemas/types.yaml#/definitions/string"
This property can not be used before virtual memory is set up and then the distinction between sv39 and sv48 is done at runtime using SATP csr property: this property is now useless, so remove it. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 13 ------------- 1 file changed, 13 deletions(-)