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dkim=none (message not signed) header.d=none;dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM6PR04MB4380.namprd04.prod.outlook.com (2603:10b6:5:a2::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23; Thu, 21 May 2020 13:46:49 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::f8b3:c124:482b:52e0]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::f8b3:c124:482b:52e0%5]) with mapi id 15.20.3000.034; Thu, 21 May 2020 13:46:49 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Subject: [PATCH 4/5] clocksource/drivers: Add CLINT timer driver Date: Thu, 21 May 2020 19:15:43 +0530 Message-Id: <20200521134544.816918-5-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200521134544.816918-1-anup.patel@wdc.com> References: <20200521134544.816918-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR01CA0073.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::15) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.30.72) by MAXPR01CA0073.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23 via Frontend Transport; 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PTR:; CAT:NONE; SFTY:; SFS:(4636009)(136003)(39860400002)(366004)(376002)(396003)(346002)(16526019)(55016002)(86362001)(316002)(26005)(1006002)(52116002)(1076003)(186003)(8886007)(54906003)(478600001)(66476007)(66946007)(55236004)(7696005)(66556008)(5660300002)(110136005)(36756003)(8676002)(2906002)(956004)(2616005)(4326008)(7416002)(8936002)(44832011); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: kp/fSbpqvcS4GQdCTnfKHxbNakaneOOMUw3pWtUOUWkIanrUMbHucIWxrQZX5BT9nBjzkh9N0yQroJLozhCuVLFRQVwm0vFqMqncXg08ox4jttfoHkefhlkxQIcglBXyYoTzlO40W4iunq06d9feL9owO0fltwa/mtFa8vOz86ggSVGZUBCV8clJ4E47HW1xWQqYh8g7XiiF50mUTX7iyw7OK2ixfvA6IP4VvmFylNM2L8yAFrsXHFYdwAOm2Eiluk8PyCRsdDbblECDjD238VgjEVH1eXcgO2USVsOOPuvNIhJe5wJeymH/ApLAuXernsUpJWSbZqpcs/aW+/c4Mv/6d7lPBVUhkvRQDxbBa2R+FZiBM3Pq4astxepVooyhRc6fHNAANWb0KWvU2dfqHHwFPb2coR+6of6p1HG3P6BuCjV1kIRXOv86Y7ICV2rB9rRCQfyTwmBKxQ6ypErDvTHeMi92zfCbQ+lXxIQsORM= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 82862357-d7e2-40e5-6055-08d7fd8d68df X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 13:46:49.0218 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DgFLJ+z7PYe595Ts64KuhEycEgXo6y9RYBL/I2ftWTBPpo8WBx0VNA9oVbWp6mVEPw/Zc7Ney8UIw6Df9l2OhA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4380 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200521_064651_846969_9AE32BF9 X-CRM114-Status: GOOD ( 21.95 ) X-Spam-Score: -1.0 (-) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-1.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.154.45 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [106.51.30.72 listed in dnsbl.sorbs.net] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Damien Le Moal , Anup Patel , Anup Patel , linux-kernel@vger.kernel.org, Atish Patra , Alistair Francis , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org The TIME CSR and SBI calls are not available in RISC-V M-mode so we add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel). Signed-off-by: Anup Patel --- drivers/clocksource/Kconfig | 10 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-clint.c | 226 ++++++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 238 insertions(+) create mode 100644 drivers/clocksource/timer-clint.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 21950d9e3e9d..ea97bf0eb09f 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -659,6 +659,16 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems. +config CLINT_TIMER + bool "Timer for the RISC-V platform" + depends on GENERIC_SCHED_CLOCK && RISCV + default y + select TIMER_PROBE + select TIMER_OF + help + This option enables the CLINT timer for RISC-V systems. The CLINT + driver is usually used for NoMMU RISC-V systems. + config CSKY_MP_TIMER bool "SMP Timer for the C-SKY platform" if COMPILE_TEST depends on CSKY diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 641ba5383ab5..dca308b5ff98 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o +obj-$(CONFIG_CLINT_TIMER) += timer-clint.o obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c new file mode 100644 index 000000000000..7fc4f145da65 --- /dev/null +++ b/drivers/clocksource/timer-clint.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + * + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a + * CLINT MMIO timer device. + */ + +#define pr_fmt(fmt) "clint: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CLINT_IPI_OFF 0 +#define CLINT_TIME_CMP_OFF 0x4000 +#define CLINT_TIME_VAL_OFF 0xbff8 + +/* CLINT manages IPI and Timer for RISC-V M-mode */ +static u32 __iomem *clint_ipi_base; +static u64 __iomem *clint_time_cmp; +static u64 __iomem *clint_time_val; +static unsigned long clint_freq; +static unsigned int clint_irq; + +static void clint_send_ipi(const unsigned long *hart_mask) +{ + u32 hartid; + + for_each_set_bit(hartid, hart_mask, NR_CPUS) + writel(1, clint_ipi_base + hartid); +} + +static void clint_clear_ipi(void) +{ + writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id())); +} + +static struct riscv_ipi_ops clint_ipi_ops = { + .ipi_inject = clint_send_ipi, + .ipi_clear = clint_clear_ipi, +}; + +#ifdef CONFIG_64BIT +#define clint_get_cycles() readq_relaxed(clint_time_val) +#else +#define clint_get_cycles() readl_relaxed(clint_time_val) +#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_time_val) + 1) +#endif + +#ifdef CONFIG_64BIT +static u64 clint_get_cycles64(void) +{ + return clint_get_cycles(); +} +#else /* CONFIG_64BIT */ +static u64 clint_get_cycles64(void) +{ + u32 hi, lo; + + do { + hi = clint_get_cycles_hi(); + lo = clint_get_cycles(); + } while (hi != clint_get_cycles_hi()); + + return ((u64)hi << 32) | lo; +} +#endif /* CONFIG_64BIT */ + +static int clint_clock_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + void __iomem *r = clint_time_cmp + + cpuid_to_hartid_map(smp_processor_id()); + + csr_set(CSR_IE, IE_TIE); + writeq_relaxed(clint_get_cycles64() + delta, r); + return 0; +} + +static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = { + .name = "clint_clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 100, + .set_next_event = clint_clock_next_event, +}; + +static u64 clint_rdtime(struct clocksource *cs) +{ + return readq_relaxed(clint_time_val); +} + +static u64 notrace clint_sched_clock(void) +{ + return readq_relaxed(clint_time_val); +} + +static struct clocksource clint_clocksource = { + .name = "clint_clocksource", + .rating = 300, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .read = clint_rdtime, +}; + +static int clint_timer_starting_cpu(unsigned int cpu) +{ + struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu); + + ce->cpumask = cpumask_of(cpu); + clockevents_config_and_register(ce, clint_freq, 200, ULONG_MAX); + + enable_percpu_irq(clint_irq, irq_get_trigger_type(clint_irq)); + return 0; +} + +static int clint_timer_dying_cpu(unsigned int cpu) +{ + disable_percpu_irq(clint_irq); + return 0; +} + +static irqreturn_t clint_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event); + + csr_clear(CSR_IE, IE_TIE); + evdev->event_handler(evdev); + + return IRQ_HANDLED; +} + +static int __init clint_timer_init_dt(struct device_node *np) +{ + int rc; + u32 i, nr_irqs; + void __iomem *base; + struct of_phandle_args oirq; + + /* + * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or + * RV_IRQ_SOFT. If it's anything else then we ignore the device. + */ + nr_irqs = of_irq_count(np); + for (i = 0; i < nr_irqs; i++) { + if (of_irq_parse_one(np, i, &oirq)) { + pr_err("%pOFP: failed to parse irq %d.\n", np, i); + continue; + } + + if ((oirq.args_count != 1) || + (oirq.args[0] != RV_IRQ_TIMER && + oirq.args[0] != RV_IRQ_SOFT)) { + pr_info("%pOFP: invalid irq %d (hwirq %d)\n", + np, i, oirq.args[0]); + return 0; + } + } + + oirq.np = riscv_of_intc_domain_node(); + oirq.args_count = 1; + oirq.args[0] = RV_IRQ_TIMER; + clint_irq = irq_create_of_mapping(&oirq); + if (!clint_irq) { + pr_err("%pOFP: could not map hwirq %d\n", np, RV_IRQ_TIMER); + return -ENODEV; + } + + base = of_iomap(np, 0); + if (!base) { + pr_err("%pOFP: could not map registers\n", np); + return -ENODEV; + } + + clint_ipi_base = base + CLINT_IPI_OFF; + clint_time_cmp = base + CLINT_TIME_CMP_OFF; + clint_time_val = base + CLINT_TIME_VAL_OFF; + clint_freq = riscv_timebase; + + pr_info("%pOFP: timer running at %ld Hz\n", np, clint_freq); + + rc = clocksource_register_hz(&clint_clocksource, clint_freq); + if (rc) { + iounmap(base); + pr_err("%pOFP: clocksource register failed [%d]\n", np, rc); + return rc; + } + + sched_clock_register(clint_sched_clock, 64, clint_freq); + + rc = request_percpu_irq(clint_irq, clint_timer_interrupt, + "clint-timer", &clint_clock_event); + if (rc) { + iounmap(base); + pr_err("registering percpu irq failed [%d]\n", rc); + return rc; + } + + rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING, + "clockevents/clint/timer:starting", + clint_timer_starting_cpu, + clint_timer_dying_cpu); + if (rc) { + free_irq(clint_irq, &clint_clock_event); + iounmap(base); + pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc); + return rc; + } + + riscv_set_ipi_ops(&clint_ipi_ops); + clint_clear_ipi(); + + return 0; +} + +TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer1, "sifive,clint-1.0.0", clint_timer_init_dt); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 57b1f8f777d9..52552492c2f2 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -132,6 +132,7 @@ enum cpuhp_state { CPUHP_AP_MIPS_GIC_TIMER_STARTING, CPUHP_AP_ARC_TIMER_STARTING, CPUHP_AP_RISCV_TIMER_STARTING, + CPUHP_AP_CLINT_TIMER_STARTING, CPUHP_AP_CSKY_TIMER_STARTING, CPUHP_AP_HYPERV_TIMER_STARTING, CPUHP_AP_KVM_STARTING,