From patchwork Tue Dec 8 07:33:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 11957751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 514F8C433FE for ; Tue, 8 Dec 2020 07:34:31 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0DE9E23A6C for ; Tue, 8 Dec 2020 07:34:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0DE9E23A6C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=v5jJHr83jPSxSSB40mNYAlfjXPmk9B+h05OQndH4qXs=; b=UFBG6uvSW/j2wSPjnXrzFndLx xArWBodijADXKuXrcm7TWnwbyxPmGDl++CITK1G0bkQ7chcRvISYBIu8ES+iUC97wRPcZ6YdsoF4m 3qITCp70Xrg84NPm7wsc2AuLkCD/3kAqZs1Dyw+9cU7keXZSs7HEi0RNp8DhBErYh3dGXFw6S+/N7 bOyfsAzgOUO8obvyQUh+XgyoXgWDc5TOtPnj0mAemKjSwB+ZEq02F3RKiGBZHtqNyTn8PEL3STlTM kgMVXYHhJWx44ku2j8JaPHW3MvNnen4Z+wh9YS2T9ItAppDEzyl1Y7Ojy/WKFkOcC18l7JZ49+4RY VWp1RgT9w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmXVt-0000Hm-CP; Tue, 08 Dec 2020 07:34:21 +0000 Received: from esa5.hgst.iphmx.com ([216.71.153.144]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmXVp-0000CB-2r for linux-riscv@lists.infradead.org; Tue, 08 Dec 2020 07:34:18 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1607412856; x=1638948856; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S1YmWmqvdIYXxQKwYnEAtpW95Vpx9w6kjXteMcQR5RY=; b=jPAIqtfQFyhbSitecLoa2b3oRqsLTyO7meejxjE87Om0wVYw/wiBjTef Od2XX90Hbv4F+VoLd+WLP6gcenSZrGEQvwMTeLGe7bZ1JnbVAEcRl9+S1 8nQ+EsMxjuqIEAhypY5lyMFzaFSyhm451hB4c9+8kfjoC32ZJGabSG9L8 gwzUmwye/y+44es8R3QPz0/5tfY2XUcFNL4JDlYH0C09FZxrLIP/55eTU J16xsn8+TjKrxiaRcqR5NXv/1puXUlqTFvmi1ge3yd7MFPc0CHhBXD0JU RtXctzVz7U8jkUXX7SHzxbFWmw3a3TB2nyb04vIy9Qm2Lm/jPnY8UMbpL Q==; IronPort-SDR: fbntNjGnCuryiAo3OTO9ilg5t6BM14sQ/wB0ELFG9jTA9nXMMdX9GEVZvAD6D5wO4fboGC8gEP JhAjfKdu0q1aXq0JxkUPB8aQENMwDDv4gW0j6EwIKJbIcmkWUYu1Hec84n5R9o3FaVixhZN2G5 Obu6V6711bivgs/NpFwjhmJ01cUPJXcRYPXqvYnxG3tdK31yeY/e8OKYlkDWIluTIUBs/AwH+d 3TiDmp+jSQJnMWgucQZtF9DQXF9fTaZ4IaPGGxL1/PptTom41UOFMPZagvcsRL6iyjUVTdHr15 2Lk= X-IronPort-AV: E=Sophos;i="5.78,401,1599494400"; d="scan'208";a="154714899" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 08 Dec 2020 15:34:16 +0800 IronPort-SDR: oHTRjLORLchktOmuEI4o0AYtHVwziHzh0hF0d1lpJI5mxDLZf+4HqhimUwwarq6E7MHU1eDnap xn592WlBvDXoLwT92WXVUUcJuaBq0Iau8= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2020 23:19:44 -0800 IronPort-SDR: RQD7EKANzywJV/HRg1j1X3bS3mlOI+gGU7eygNLNiakd8330VcLccRz8OKJQYvmBK8JyAnwEls Yb6KPydp+Iag== WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.173]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Dec 2020 23:34:15 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Subject: [PATCH v5 08/21] dt-bindings: reset: Document canaan, k210-rst bindings Date: Tue, 8 Dec 2020 16:33:42 +0900 Message-Id: <20201208073355.40828-9-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201208073355.40828-1-damien.lemoal@wdc.com> References: <20201208073355.40828-1-damien.lemoal@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201208_023417_317164_F0FAB5F3 X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Anderson Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Document the device tree bindings for the Canaan Kendryte K210 SoC reset controller driver in Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml. The header file include/dt-bindings/reset/k210-rst.h is added to define all possible reset lines of the SoC. Signed-off-by: Damien Le Moal --- .../bindings/reset/canaan,k210-rst.yaml | 40 ++++++++++++++++++ include/dt-bindings/reset/k210-rst.h | 42 +++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml create mode 100644 include/dt-bindings/reset/k210-rst.h diff --git a/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml new file mode 100644 index 000000000000..53e4ede9c0bd --- /dev/null +++ b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K210 Reset Controller Device Tree Bindings + +maintainers: + - Damien Le Moal + +description: | + Canaan Kendryte K210 reset controller driver which supports the SoC + system controller supplied reset registers for the various peripherals + of the SoC. The K210 reset controller node must be defined as a child + node of the K210 system controller node. + + See also: + - dt-bindings/reset/k210-rst.h + +properties: + compatible: + const: canaan,k210-rst + + '#reset-cells': + const: 1 + +required: + - '#reset-cells' + - compatible + +additionalProperties: false + +examples: + - | + #include + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h new file mode 100644 index 000000000000..883c1aed50e8 --- /dev/null +++ b/include/dt-bindings/reset/k210-rst.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +/* + * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. + * Taken from Kendryte SDK (kendryte-standalone-sdk). + */ +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */