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07 Jan 2021 01:12:21 -0800 IronPort-SDR: D/Knafnf+hm5DcoIAHYkKbWfhimscqE4QSGo3S2M2O+n3VUcQpS+4ojoLeHyP8B9OyAF/F4kbQ NqBGYWOhSBtmY5WGTSmIozXmNdRdpuGmp2fjHgGC/zxeHCs4eqjjcoRjj5fkgLmihhAvgSkixm 70hyFaAOj7wxpn1V6vqucV4/KOiocJdfHFEftb5IPo8hyi5epUu5EtdHR1Hm01SklVW9pkC1VR IiNTlhmvWDfv0w/GxMhZ+edhT4S/ULvwrHdxmpcgnqWekAauPDEhOr92rxlovhEUM01bOhWSPF M4s= WDCIronportException: Internal Received: from usa002483.ad.shared (HELO jedi-01.hgst.com) ([10.86.62.136]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Jan 2021 01:27:30 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32 Date: Thu, 7 Jan 2021 01:26:51 -0800 Message-Id: <20210107092652.3438696-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107092652.3438696-1-atish.patra@wdc.com> References: <20210107092652.3438696-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210107_042735_457329_9EEA39DA X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Anup Patel , linux-riscv@lists.infradead.org, Atish Patra , Palmer Dabbelt , Paul Walmsley , Nick Kossifidis , Andrew Morton , Ard Biesheuvel , Mike Rapoport Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock allocation if it is requested to be aligned with SMP_CACHE_BYTES. Signed-off-by: Atish Patra Tested-by: Geert Uytterhoeven Reviewed-by: Anup Patel --- arch/riscv/include/asm/cache.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9b58b104559e..c9c669ea2fe6 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,7 +7,11 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#ifdef CONFIG_64BIT #define L1_CACHE_SHIFT 6 +#else +#define L1_CACHE_SHIFT 5 +#endif #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)