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11 Jan 2021 15:30:06 -0800 IronPort-SDR: S4/lzpttx6/ZOnuXtMd2AXORHB8tLqvAqVfTYA8r+mdnyUCj7ItefrtrKECOgJE02m8nayn5A6 CoVXlHknaU3TfcNc2Uwee8WCnSvWmEpd5tkfUQ3TEA+uIGX6197ACGDOBZkKGdI39K4Oi/0Por UgnAQY6aaf9JjD83vanUpc2jsIUtaElnPKvWUN8WujGXNRDtUUybiUa/b42T7LSb5TPIn/VFEZ /kqrRJVFAxSyq60AiEaVu8jxdvKhccWAJDDroZZMKRxusckMqvhm0DW29VLl65CpImj5UVpZ5t +rE= WDCIronportException: Internal Received: from usa002483.ad.shared (HELO jedi-01.hgst.com) ([10.86.62.194]) by uls-op-cesaip02.wdc.com with ESMTP; 11 Jan 2021 15:45:20 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32 Date: Mon, 11 Jan 2021 15:45:03 -0800 Message-Id: <20210111234504.3782179-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111234504.3782179-1-atish.patra@wdc.com> References: <20210111234504.3782179-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210111_184527_202297_15E68916 X-CRM114-Status: GOOD ( 10.08 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Anup Patel , linux-riscv@lists.infradead.org, Atish Patra , Geert Uytterhoeven , Paul Walmsley , Palmer Dabbelt , Andrew Morton , Ard Biesheuvel , Mike Rapoport Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock allocation if it is requested to be aligned with SMP_CACHE_BYTES. Reviewed-by: Anup Patel Tested-by: Geert Uytterhoeven (on vexriscv) Signed-off-by: Atish Patra --- arch/riscv/include/asm/cache.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9b58b104559e..c9c669ea2fe6 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,7 +7,11 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#ifdef CONFIG_64BIT #define L1_CACHE_SHIFT 6 +#else +#define L1_CACHE_SHIFT 5 +#endif #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)