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17 Jan 2021 17:45:42 -0800 IronPort-SDR: ZNZ4rHBX0qI+Fsgead47p1q+2c+soqv/N+kwIHlIPxgOl55R9tSz4jjC1OEoV4Q36B0Zw7vMKV 5XY5En1Trl8IehEugWK88yYL0vE60pzWVZ1HWkfbQfg+F0cqqAkDtPvszTtQRNMo7lq6apl16P 3b+dsjMytw/oC0sXZJdypq3MudMZTS6zKrppcpRH0YydKP3H3vy6w9DzKhQGFmTJso4YG59DwF pZ7y8+FbX3/OzuEKn3Cvrj4/nZgXnm+ayUhLCeiL/ArS9e7o/G7cnQM/PuyAEmaJ1n/GsXBodA lm4= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:05 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Subject: [PATCH v13 05/17] dt-bindings: update sifive plic compatible string Date: Mon, 18 Jan 2021 11:02:32 +0900 Message-Id: <20210118020244.103451-6-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210117_210306_153058_A17CF526 X-CRM114-Status: UNSURE ( 9.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , devicetree@vger.kernel.org, Paul Walmsley , Sean Anderson Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the compatible string "canaan,k210-plic" to the Sifive plic bindings to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan Kendryte K210 SoC. The description is also updated to reflect this change, that is, that SoCs from other vendors may also use this plic implementation. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../sifive,plic-1.0.0.yaml | 20 ++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index b9a61c9f7530..3db86d329e1e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Platform-Level Interrupt Controller (PLIC) description: - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller - (PLIC) high-level specification in the RISC-V Privileged Architecture - specification. The PLIC connects all external interrupts in the system to all - hart contexts in the system, via the external interrupt source in each hart. + SiFive other RISC-V and other SoCs include an implementation of the + Platform-Level Interrupt Controller (PLIC) high-level specification in + the RISC-V Privileged Architecture specification. The PLIC connects all + external interrupts in the system to all hart contexts in the system, via + the external interrupt source in each hart. A hart context is a privilege mode in a hardware execution thread. For example, in an 4 core system with 2-way SMT, you have 8 harts and probably at least two @@ -41,9 +42,14 @@ maintainers: properties: compatible: - items: - - const: sifive,fu540-c000-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - const: sifive,fu540-c000-plic + - const: sifive,plic-1.0.0 + + - items: + - const: canaan,k210-plic + - const: sifive,plic-1.0.0 reg: maxItems: 1