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07 Feb 2021 14:55:03 -0800 IronPort-SDR: XHHY8qAqUus4XDbOInV7na7FHby51DXVeI/QQvUGbg+HiRWwmBII0WTgNv6rHy9EEV2LLkFq+1 veFL4igoAQVkKCsGFSOkhxNdG6y8ba6knVfEtzR/DzkADOuaA1XAAhwjsGsDx77sVw7Bb7RX9p DjKremtY01tdHYwpKFGufJMdUBE/fu6SOaQwT1tacR2akyeBpp6RiCo+FDxWNBqsf8w/uRCItr y9YfeQ1Vqgxps4HimSiUk+TqV2uobwOKgk+VF32rpLnrWOcUKQJMhsZfOf1cFEg4qrUp3SHJ6o xNw= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.69]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Feb 2021 15:13:07 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Subject: [PATCH v17 04/16] dt-bindings: update sifive plic compatible string Date: Mon, 8 Feb 2021 08:12:44 +0900 Message-Id: <20210207231256.115130-5-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210207231256.115130-1-damien.lemoal@wdc.com> References: <20210207231256.115130-1-damien.lemoal@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210207_181308_890671_E7C7F7F7 X-CRM114-Status: GOOD ( 10.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , Anup Patel , Sean Anderson , Atish Patra , Paul Walmsley Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the compatible string "canaan,k210-plic" to the Sifive plic bindings to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan Kendryte K210 SoC. The description is also updated to reflect this change, that is, that SoCs from other vendors may also use this plic implementation. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Acked-by: Rob Herring --- .../interrupt-controller/sifive,plic-1.0.0.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index b9a61c9f7530..08d5a57ce00f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Platform-Level Interrupt Controller (PLIC) description: - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller - (PLIC) high-level specification in the RISC-V Privileged Architecture - specification. The PLIC connects all external interrupts in the system to all - hart contexts in the system, via the external interrupt source in each hart. + SiFive SoCs and other RISC-V SoCs include an implementation of the + Platform-Level Interrupt Controller (PLIC) high-level specification in + the RISC-V Privileged Architecture specification. The PLIC connects all + external interrupts in the system to all hart contexts in the system, via + the external interrupt source in each hart. A hart context is a privilege mode in a hardware execution thread. For example, in an 4 core system with 2-way SMT, you have 8 harts and probably at least two @@ -42,7 +43,9 @@ maintainers: properties: compatible: items: - - const: sifive,fu540-c000-plic + - enum: + - sifive,fu540-c000-plic + - canaan,k210-plic - const: sifive,plic-1.0.0 reg: