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This works if the hardware does not implement the TIME CSR and traps to the firmware. The spec however does allow a hardware implementation to redirect the CSR access to the memory-mapped MTIME CSR, and if this is performed it will check {M,S}COUNTEREN CSR to see if it is allowed. To prevent unhandled illegal instruction fault on these platforms, we can request these CSRs to be enabled in U-mode. For platforms that does not support the TIME CSR to MTIME CSR conversion, they will hardwire corresponding bit in COUNTEREN to zero and this would be a no-op. Signed-off-by: Gary Guo --- arch/riscv/kernel/head.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 0a4e81b8dc79..5a7a62190342 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -190,6 +190,9 @@ ENTRY(_start_kernel) .align 2 pmp_done: + /* Allow user-mode to access time CSR */ + csrw, CSR_MCOUNTEREN, 2 + /* * The hartid in a0 is expected later on, and we have no firmware * to hand it to us. @@ -197,6 +200,9 @@ pmp_done: csrr a0, CSR_MHARTID #endif /* CONFIG_RISCV_M_MODE */ + /* Allow user-mode to access time CSR */ + csrw CSR_SCOUNTEREN, 2 + /* Load the global pointer */ .option push .option norelax