diff mbox series

[RESEND,v2,5/5] riscv: dts: sifive: add missing compatible for plic

Message ID 20210920130412.145231-2-krzysztof.kozlowski@canonical.com (mailing list archive)
State New, archived
Headers show
Series [RESEND,v2,1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible | expand

Commit Message

Krzysztof Kozlowski Sept. 20, 2021, 1:04 p.m. UTC
Add proper compatible for Platform-Level Interrupt Controller to silence
dtbs_check warnings:

  interrupt-controller@c000000: compatible: ['sifive,plic-1.0.0'] is too short

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. None
---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alexandre Ghiti Oct. 12, 2021, 4:49 a.m. UTC | #1
On Mon, Sep 20, 2021 at 3:06 PM Krzysztof Kozlowski
<krzysztof.kozlowski@canonical.com> wrote:
>
> Add proper compatible for Platform-Level Interrupt Controller to silence
> dtbs_check warnings:
>
>   interrupt-controller@c000000: compatible: ['sifive,plic-1.0.0'] is too short
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
> ---
>
> Changes since v1:
> 1. None
> ---
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> index 7db861053483..0655b5c4201d 100644
> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> @@ -141,7 +141,7 @@ soc {
>                 ranges;
>                 plic0: interrupt-controller@c000000 {
>                         #interrupt-cells = <1>;
> -                       compatible = "sifive,plic-1.0.0";
> +                       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
>                         reg = <0x0 0xc000000 0x0 0x4000000>;
>                         riscv,ndev = <53>;
>                         interrupt-controller;
> --
> 2.30.2
>
>

This looks good to me, you can add:

Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>

Thanks,

Alex

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> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db861053483..0655b5c4201d 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -141,7 +141,7 @@  soc {
 		ranges;
 		plic0: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;
-			compatible = "sifive,plic-1.0.0";
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
 			riscv,ndev = <53>;
 			interrupt-controller;